Packing odd bytes from two source registers of packed data
    33.
    发明授权
    Packing odd bytes from two source registers of packed data 有权
    从打包数据的两个源寄存器中包装奇数字节

    公开(公告)号:US09015453B2

    公开(公告)日:2015-04-21

    申请号:US13730848

    申请日:2012-12-29

    申请人: Intel Corporation

    IPC分类号: G06F9/315 G06F9/30 G06F7/499

    摘要: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

    摘要翻译: 一种装置包括指令解码器,第一和第二源寄存器以及耦合到解码器的电路,用于从源寄存器接收压缩数据,并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中,其中与第一打包数据元素相邻的第二打包数据元素,与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。

    APPARATUS AND METHOD FOR SLIDING WINDOW DATA GATHER
    36.
    发明申请
    APPARATUS AND METHOD FOR SLIDING WINDOW DATA GATHER 审中-公开
    用于滑动数据窗口的装置和方法

    公开(公告)号:US20140281369A1

    公开(公告)日:2014-09-18

    申请号:US13997656

    申请日:2011-12-23

    申请人: Ashish Jha

    发明人: Ashish Jha

    IPC分类号: G06F9/30

    摘要: An apparatus and method are described for fetching and storing a plurality of portions of a data stream into a plurality of registers. For example, a method according to one embodiment includes the following operations: determining a set of N vector registers into which to read N designated portions of a data stream stored in system memory; determining the system memory addresses for each of the N designated portions of the data stream; fetching the N designated portions of the data stream from the system memory at the system memory addresses; and storing the N designated portions of the data stream into the N vector registers.

    摘要翻译: 描述了一种用于将数据流的多个部分取出并存储到多个寄存器中的装置和方法。 例如,根据一个实施例的方法包括以下操作:确定一组N个向量寄存器,用于读取存储在系统存储器中的数据流的N个指定部分; 确定数据流的N个指定部分中的每一个的系统存储器地址; 在系统存储器地址处从系统存储器取出数据流的N个指定部分; 并将数据流的N个指定部分存储到N个向量寄存器中。

    Packing lower half bits of signed data elements in two source registers in a destination register with saturation
    37.
    发明授权
    Packing lower half bits of signed data elements in two source registers in a destination register with saturation 有权
    在目标寄存器中的两个源寄存器中将带符号数据元素的下半位包装为饱和

    公开(公告)号:US08838946B2

    公开(公告)日:2014-09-16

    申请号:US13730849

    申请日:2012-12-29

    申请人: Intel Corporation

    IPC分类号: G06F9/30

    摘要: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

    摘要翻译: 一种装置包括指令解码器,第一和第二源寄存器以及耦合到解码器的电路,用于从源寄存器接收压缩数据,并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中,其中与第一打包数据元素相邻的第二打包数据元素,与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。

    DOT PRODUCT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    38.
    发明申请
    DOT PRODUCT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
    产品处理器,方法,系统和说明

    公开(公告)号:US20140195783A1

    公开(公告)日:2014-07-10

    申请号:US13977094

    申请日:2011-12-29

    IPC分类号: G06F9/30

    摘要: A method of an aspect includes receiving a dot product instruction. The dot product instruction indicates a first source packed data including at least four data elements, indicates a second source packed data including at least eight data elements, and indicates a destination storage location. A result packed data is stored in the destination storage location in response to the dot product instruction. The result includes a plurality of data elements that each includes a dot product result. Each of the dot product results includes a sum of products of the at least four data elements of the first source packed data with corresponding data elements in a different subset of at least four data elements of the second source packed data. Other methods, apparatus, systems, and instructions are disclosed.

    摘要翻译: 一方面的方法包括接收点积指令。 点产品指令指示包括至少四个数据元素的第一源打包数据,指示包括至少八个数据元素的第二源打包数据,并且指示目的地存储位置。 响应于点积指令,结果打包数据被存储在目的地存储位置。 结果包括多个数据元素,每个数据元素包括点积结果。 每个点积结果包括第一源打包数据的至少四个数据元素与第二源打包数据的至少四个数据元素的不同子集中的相应数据元素的乘积之和。 公开了其它方法,装置,系统和指令。

    TRACKING AND RECLAIMING PHYSICAL REGISTERS
    39.
    发明申请
    TRACKING AND RECLAIMING PHYSICAL REGISTERS 审中-公开
    跟踪和回收物理寄存器

    公开(公告)号:US20140129804A1

    公开(公告)日:2014-05-08

    申请号:US13667354

    申请日:2012-11-02

    申请人: John M. King

    发明人: John M. King

    IPC分类号: G06F15/76

    摘要: A method and apparatus for tracking and reclaiming physical registers is presented. Some embodiments of the apparatus include rename logic configurable to map architectural registers to physical registers. The rename logic is configurable to bypass allocation of a physical register to an architectural register when information to be written to the architectural register satisfies a bypass condition. Some embodiments of the apparatus also include a plurality of first bits associated with the architectural registers. The rename logic is configurable to set one of the first bits to indicate that allocation of a physical register to the corresponding architectural register has been bypassed.

    摘要翻译: 提出了一种跟踪和回收物理寄存器的方法和装置。 该装置的一些实施例包括可配置以将架构寄存器映射到物理寄存器的重命名逻辑。 当要写入架构寄存器的信息满足旁路条件时,重命名逻辑可以配置为绕过物理寄存器的分配到架构寄存器。 装置的一些实施例还包括与架构寄存器相关联的多个第一位。 重命名逻辑可配置为设置第一位中的一个,以指示物理寄存器分配给对应的架构寄存器已被绕过。