公开(公告)号：US07061931B2

公开(公告)日：2006-06-13

申请号：US10925439

申请日：2004-08-25

Applicant: Moshe Voloshin ,  Mark D. Cavaro

Inventor： Moshe Voloshin ,  Mark D. Cavaro

IPC: H04L12/40 ,  H04J3/06

CPC classification number: H04J3/06 ,  H04L12/40

Abstract: Provided is a synchronous stack bus repeater system for a computer network. The system includes a plurality of stacked repeaters, a stack bus linking the repeaters, and a single clock to which the plurality of repeaters is synchronized. The synchronization of the stack bus eliminates several time-consuming communications required between devices operating with different clocks on an asynchronous bus and makes it possible to satisfy the 46 bit time repeater maximum latency required of a Class II repeater according to the IEEE 802.3 standard.

Abstract translation: 提供了一种用于计算机网络的同步堆叠总线中继器系统。 该系统包括多个堆叠的中继器，连接中继器的堆栈总线和多个中继器同步的单个时钟。 堆叠总线的同步消除了在异步总线上以不同时钟运行的设备之间需要的几次耗时的通信，并且可以满足根据IEEE 802.3标准的Class II中继器所需的46位时间中继器最大等待时间。

公开(公告)号：US06807151B1

公开(公告)日：2004-10-19

申请号：US09536515

申请日：2000-03-27

Applicant: Thusitha Jayawardena

Inventor： Thusitha Jayawardena

IPC: H04J306

CPC classification number: H04J3/14 ,  H04J3/06 ,  H04L7/042

Abstract: Group-wise testing of the clocks arriving at a switching office is undertaken by multiplexing the clocks onto a single line and developing a signal therefrom that is indicative of a problem, if it exists, in any of the component signals that were multiplexed. In one embodiment, the developed signal is a gated portion of the multiplexed signal. That signal is integrated over an integration frame and compared to the integrated signal of another integration frame. A difference between the two compared signals indicates that at least one of the clocks is out of frequency synch. Subsequent tests identify the offending clock, or clocks.

Abstract translation: 通过对到达交换局的时钟进行分组测试，通过将时钟复用到单个线路上并从其中开发指示在多路复用的任何分量信号中的问题的信号（如果存在）。 在一个实施例中，显影信号是多路复用信号的选通部分。 该信号在集成框架上集成，并与另一个集成框架的集成信号进行比较。 两个比较信号之间的差异表示至少一个时钟频率同步。 随后的测试识别违规时钟或时钟。

公开(公告)号：US06788753B1

公开(公告)日：2004-09-07

申请号：US09570371

申请日：2000-05-12

Applicant: Christopher T. Brown

Inventor： Christopher T. Brown

IPC: H04L700

CPC classification number: G11B27/3027 ,  G11B20/14 ,  G11B20/18 ,  G11B2020/1476 ,  H04J3/06

Abstract: A timing circuit used in reading disc media or other dada includes multiple sync detection circuits. In the event that an active sync detection circuit fails to detect sync signals within predefined parameters, a different one of the sync detection circuits searches for a sync pattern. Uniquely definable sequences of sync patterns are used to determine a position of sync patterns within a sector of data.

Abstract translation: 用于读取盘媒体或其他数据的定时电路包括多个同步检测电路。 在活动同步检测电路未能检测到预定义参数内的同步信号的情况下，不同的同步检测电路搜索同步模式。 使用唯一可定义的同步模式序列来确定数据扇区内同步模式的位置。

公开(公告)号：US5844907A

公开(公告)日：1998-12-01

申请号：US685746

申请日：1996-07-24

Applicant: Tatsuya Uchiki ,  Toshiharu Kojima

Inventor： Tatsuya Uchiki ,  Toshiharu Kojima

IPC: H04L27/22 ,  H04J3/06 ,  H04L1/02 ,  H04L1/08 ,  H04L7/00 ,  H04L7/08

CPC classification number: H04J3/06

Abstract: A synchronization determining method and circuit for determining a synchronization state of a multiplexed data stream derived by multiplexing a plurality of data streams having the same contents with a time lag provided therebetween, wherein the synchronization determining circuit establishes synchronization without decreasing transmission efficiency, generating incorrect code sequences, or increasing overall circuit scale. In each embodiment of the present invention, synchronization is established without using synchronization words. Because synchronization is achieved without feedback loop delay, incorrectly decoded sequences are not generated for a period of time before synchronization is established. Also, because no maximum pass metric state detecting circuit is required, circuit scale, power consumption, and operating speed can be improved.

Abstract translation: 一种同步确定方法和电路，用于确定通过多路复用具有相同内容的多个数据流而产生的多路复用数据流的同步状态，其中同步确定电路在不降低传输效率的情况下建立同步而产生不正确的代码 序列，或增加总体电路规模。 在本发明的每个实施例中，在不使用同步字的情况下建立同步。 由于在没有反馈环路延迟的情况下实现同步，因此在建立同步之前的一段时间内不会产生错误解码的序列。 此外，由于不需要最大通过度量状态检测电路，因此可以提高电路规模，功耗和运行速度。

公开(公告)号：US5463627A

公开(公告)日：1995-10-31

申请号：US200592

申请日：1994-02-23

Applicant: Akihiko Matsuoka ,  Hiroshi Ohnishi ,  Yoshinori Kunieda ,  Kouei Misaizu ,  Yuuri Yamamoto

Inventor： Akihiko Matsuoka ,  Hiroshi Ohnishi ,  Yoshinori Kunieda ,  Kouei Misaizu ,  Yuuri Yamamoto

IPC: H03L7/085 ,  H04J3/06 ,  H04L7/033 ,  H04L7/04 ,  H04L7/08

CPC classification number: H04L7/042 ,  H03L7/085 ,  H04J3/06 ,  H04L7/0331 ,  H04L7/08

Abstract: In a frame synchronizing apparatus for a receiver apparatus of a digital data radio communications system in which data are transmitted in frame periods with a fixed data sequence contained each frame, a data correlation circuit obtains successive sequences of values of vector difference between vector values constituting a demodulated digital baseband signal, and successively compares these sequences with a fixed vector difference sequence corresponding to the fixed data sequence, to derive a correlation signal substantially unaffected by any phase rotation in the baseband signal. A frame synchronizing circuit formed as a PLL for generating a frame synchronizing signal, includes a phase comparator which periodically indicates whether a detected phase difference between the correlation signal and frame synchronizing signal is effectively zero, positive or negative, and a counter holding a count value indicating a cumulative phase error between these signals. So long as the detected phase differences are successively effectively zero and the cumulative phase error is sufficiently small, the phase of the frame synchronizing signal is held unchanged, thereby achieving a high degree of phase stability.

Abstract translation: 在数字数据无线电通信系统的接收机装置的帧同步装置中，数据在具有包含每一帧的固定数据序列的帧周期中被发送，数据相关电路获得构成矢量的矢量值之间的向量差的值的连续序列 解调的数字基带信号，并且将这些序列与对应于固定数据序列的固定向量差异序列连续地进行比较，以导出基本上不受基带信号中的任何相位旋转影响的相关信号。 形成为用于产生帧同步信号的PLL的帧同步电路包括周期性地指示相关信号和帧同步信号之间的检测到的相位差是否为零或正的负相位的相位比较器，以及保持计数值的计数器 表示这些信号之间的累积相位误差。 只要检测到的相位差连续有效地为零并且累积相位误差足够小，则帧同步信号的相位保持不变，从而实现高度的相位稳定性。

公开(公告)号：US5386436A

公开(公告)日：1995-01-31

申请号：US879819

申请日：1992-05-07

Applicant: Shinichi Kawada ,  Keiichiro Hijino ,  Hiroshi Wada ,  Masahisa Iida

Inventor： Shinichi Kawada ,  Keiichiro Hijino ,  Hiroshi Wada ,  Masahisa Iida

IPC: H04B14/06 ,  H03M3/04 ,  H03M7/38 ,  H03M13/33 ,  H04J3/06 ,  H04L7/00 ,  H04L7/02

CPC classification number: H04L7/0054 ,  H03M13/33 ,  H03M3/042 ,  H04J3/06

Abstract: In a synchronization system for use in a digital transmission system in which an encoded digital transmission signal at least part of bits of which have specific statistic characteristics is transmitted, a digital transmission signal received by a decoder within a digital transmission apparatus at a receiving end is subjected to a decoding processing in units of samples on the basis of a synchronous input signal. The digital transmission apparatus at the receiving end includes a monitor for monitoring internal states of the decoder which vary between a synchronous state and an asynchronous state owing to the statistic characteristics of the digital transmission signal, a synchronization detector for determining whether the digital transmission system is in the synchronous state based on an output of the monitor, and a phase shifter for shifting a relative phase of the digital transmission signal against a synchronous input signal supplied to the decoder, one bit by one on the digital transmission signal in units of samples, in the case that a determination result of the synchronization detector indicates the asynchronous state.

Abstract translation: 在用于数字传输系统的同步系统中，其中至少部分比特具有特定统计特性的编码数字传输信号被发送到接收端的数字传输装置内的解码器接收到的数字传输信号， 以基于同步输入信号的样本为单位进行解码处理。 接收端的数字发送装置包括：监视器，用于监视由于数字传输信号的统计特性而在同步状态和异步状态之间变化的解码器的内部状态;同步检测器，用于确定数字传输系统是否为 基于监视器的输出的同步状态，以及移相器，用于相对于提供给解码器的同步输入信号相对于数字传输信号以样本为单位移位相对相位， 在同步检测器的确定结果指示异步状态的情况下。

公开(公告)号：US5383188A

公开(公告)日：1995-01-17

申请号：US138006

申请日：1993-10-19

Applicant: Naoto Shigemoto

Inventor： Naoto Shigemoto

IPC: H04J3/06 ,  H04L7/00 ,  H04L7/04 ,  H04L7/10 ,  H04L25/40

CPC classification number: H04J3/06 ,  H04L7/10 ,  H04L7/0083 ,  H04L7/04

Abstract: A clock phase signal of each time slot of a TDM signal is stored into a corresponding memory location and a clock phase signal of a subsequent time slot is read from a memory location corresponding to the subsequent time slot for recovering clock pulses. A decoder is synchronized with the clock pulses for decoding an encoded digital signal of each time slot to produce a decoded signal. The error rate of the decoded signal of each time slot is detected and compared with a prescribed value. When the detected error rate is determined to be higher than the prescribed value, the write operation of the memory is disabled to prevent the clock phase signal stored in a memory location corresponding to the decoded signal from being overwritten with a subsequent clock phase signal.

Abstract translation: TDM信号的每个时隙的时钟相位信号被存储到对应的存储器位置中，并且从对应于后续时隙的存储器位置读取后续时隙的时钟相位信号，以恢复时钟脉冲。 解码器与用于解码每个时隙的编码数字信号的时钟脉冲同步以产生解码信号。 检测每个时隙的解码信号的错误率并将其与规定值进行比较。 当检测到的错误率被确定为高于规定值时，禁止存储器的写入操作，以防止存储在与解码信号相对应的存储器位置中的时钟相位信号被随后的时钟相位信号重写。

公开(公告)号：US4151373A

公开(公告)日：1979-04-24

申请号：US831297

申请日：1977-09-07

Applicant: Walter R. Widmer ,  Hans-Jorg Klemenz ,  Pierre Schmid

Inventor： Walter R. Widmer ,  Hans-Jorg Klemenz ,  Pierre Schmid

IPC: H04J3/07 ,  H04J3/06 ,  H04J3/12 ,  H04L7/00

CPC classification number: H04J3/12 ,  H04J3/06 ,  H04J3/0602

Abstract: A system for inserting extra-information bits into a bit sequence to be transmitted over a transmission channel and for suppressing such bits from the transmitted bit sequence, the system having an inserter at the transmitting end and a suppressor at the receiving end, the inserter converting an input bit sequence which it receives at a first repetition frequency into a second repetition frequency which is higher to correspond to the inserted extra bits, by the insertion of m extra bits per m.k.n bits of the input bit sequence k, n and m denoting integers which are greater than zero, the suppressor restoring the original input bit sequence at the first repetition frequency and the extra-information bits from the output bit sequence which it receives from the transmitter at the second repetition frequency, the inserter comprising a first repetition frequency generator which derives the output bit sequence repetition frequency from the input sequence repetition frequency and complies with the condition n.k.gtoreq. 50.

Abstract translation: 一种用于将多个信息比特插入到要在传输信道上发送的比特序列并用于从发送的比特序列抑制这些比特的系统，该系统在发送端具有一个插入器，在接收端具有一个抑制器，该插入器转换 通过在输入比特序列k，n和m表示整数的mkn比特中插入m个额外比特，将以第一重复频率接收的输入比特序列转换成高于对应于插入的额外比特的第二重复频率 其大于零，所述抑制器以所述第一重复频率恢复所述原始输入比特序列和从所述发射机以所述第二重复频率接收的所述输出比特序列的所述额外信息比特，所述插入器包括第一重复频率发生器 其从输入序列重复频率导出输出位序列重复频率并符合要求 h条件n.k> / = 50。

公开(公告)号：US3990009A

公开(公告)日：1976-11-02

申请号：US558220

申请日：1975-03-14

Applicant: George Howard Lentz

Inventor： George Howard Lentz

IPC: H04B1/74 ,  H04B7/17 ,  H04J3/06 ,  H04J3/07 ,  H04L1/02 ,  H04L25/14 ,  H03K13/32

CPC classification number: H04L25/14 ,  H04B1/74 ,  H04J3/06 ,  H04J3/07 ,  H04L1/02

Abstract: In a digital transmission system of the type which employs cross-polarized radio channels, the failure of a transmitter associated with a particular channel can cause an undesired signal cross-over into the receiver of the failed channel. According to the instant invention, each channel in the system is uniquely encoded by a combination of bitstream inversion and bitstream delay at the head end of the system. Thus, if a signal crossover occurs an excessive number of parity violations are detected in the failed channel and a switch to a protection channel is requested.

Abstract translation: 在采用交叉极化无线电信道的数字传输系统中，与特定信道相关联的发射机的故障可能导致不期望的信号交叉到失败信道的接收机中。 根据本发明，系统的前端的比特流反转和比特流延迟的组合对系统中的每个信道进行唯一的编码。 因此，如果发生信号交叉，则在故障通道中检测到过多的奇偶校验违例，并且请求切换到保护信道。

公开(公告)号：US3916107A

公开(公告)日：1975-10-28

申请号：US29567472

申请日：1972-10-06

Applicant: BELL TELEPHONE LABOR INC

Inventor： MCDONALD HENRY STANTON

IPC: H03M7/00 ,  H04J3/00 ,  H04J3/06 ,  H04L5/22 ,  H04L25/05

CPC classification number: H03M7/3048 ,  H04J3/00 ,  H04J3/06 ,  H04J3/062 ,  H04L25/05

Abstract: Time division multiplexed pulse code modulated digital character signals received from a transmission medium are demultiplexed and converted into respective delta modulation signals in accordance with a first set of time base information derived from the pulse code modulated signals. This operation removes pulse code character and time division frame time restrictions. The delta modulated signals are recoded to a predetermined pulse code modulated format, such as differential pulse code modulation, in accordance with a second set of time base information for appropriate further processing or transmission.