公开(公告)号：US20220208559A1

公开(公告)日：2022-06-30

申请号：US17137562

申请日：2020-12-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ai-Tee Ang ,  I-Tseng Lee

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/67 ,  H01L25/07

Abstract: Chip manufacturing, including: assembling at least two chips on a layer; and applying mold compound on the at least two chips to the sides and bottom including flowing around interconnects, thereby leaving the top of each of the at least two chips exposed.

公开(公告)号：US20220197826A1

公开(公告)日：2022-06-23

申请号：US17129786

申请日：2020-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： SeyedMohammad SeyedzadehDelcheh

IPC: G06F12/14 ,  G06F12/0895 ,  G06F21/55

Abstract: A method and apparatus of protecting a memory from a write attack includes dividing a cacheline of memory into a plurality of sub-blocks. A codeword is generated from at least one sub-block of the plurality of sub-blocks and a complement of the at least one sub-block. One of the generated codewords is selected, wherein the selected codeword is used for storage in memory.

公开(公告)号：US20220197524A1

公开(公告)日：2022-06-23

申请号：US17128844

申请日：2020-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Max RUTTENBERG ,  Vedula Venkata Srikant BHARADWAJ ,  Yasuko ECKERT ,  Mark H. OSKIN ,  Anthony GUTIERREZ

IPC: G06F3/06

Abstract: A processor sets memory timing parameters based on a profile of a workload to be executed at the processor and based on a thermal budget associated with the processor. For a given workload and amount of available thermal headroom, as indicated by a detected temperature, the processor adjusts one or more of the memory timing parameters according to the workload profile. The processor is thereby able to tailor the memory timing parameters according to the memory access behavior of the workload, improving overall processing efficiency.

公开(公告)号：US20220189897A1

公开(公告)日：2022-06-16

申请号：US17118126

申请日：2020-12-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAHUL AGARWAL

IPC: H01L23/00 ,  H01L23/528

Abstract: A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.

公开(公告)号：US20220189112A1

公开(公告)日：2022-06-16

申请号：US17121965

申请日：2020-12-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nishank PATHAK

IPC: G06T17/20 ,  G06T15/00

Abstract: A processing system includes hull shader circuitry that launches thread groups including one or more primitives. The hull shader circuitry also generates tessellation factors that indicate subdivisions of the primitives. The processing system also includes throttling circuitry that estimates a primitive launch time interval for the domain shader based on the tessellation factors and selectively throttles launching of the thread groups from the hull shader circuitry based on the primitive launch time interval of the domain shader and a hull shader latency. In some cases, the throttling circuitry includes a first counter that is incremented in response to launching a thread group from the buffer and a second counter that modifies the first counter based on a measured latency of the domain shader.

公开(公告)号：US20220188180A1

公开(公告)日：2022-06-16

申请号：US17131512

申请日：2020-12-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Philip Ng ,  Buheng Xu

IPC: G06F11/07 ,  G06F9/46 ,  G06F13/38

Abstract: A method and system for recording and logging errors in a computer system includes reading first error handling information with respect to a transaction. The first error handling information is stored in a first component, and based upon a condition of the storage in the first component, an oldest error information is evicted from the first component.

公开(公告)号：US20220187896A1

公开(公告)日：2022-06-16

申请号：US17568354

申请日：2022-01-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Greg Sadowski

IPC: G06F1/3228 ,  G06F1/3296 ,  G06F11/34 ,  G06N20/00

Abstract: A processing unit includes a plurality of components configured to execute instructions and a controller. The controller is configured to determine a power consumption of the processing unit, determine a waiting status of the processing unit based on waiting statuses of components, and selectively modify an operating state of the processing unit based on the waiting status and the power consumption of the processing unit. In some cases, the operating state is modified in response to a percentage of the components that are waiting for an action to complete being below a threshold percentage and the power consumption of the processing unit being below a power limit. In some cases, the controller identifies a pattern in the power consumption by the processing unit and modifies the operating state of the processing unit to increase the power consumption of the processing unit based on the pattern identified by the controller.

公开(公告)号：US11360891B2

公开(公告)日：2022-06-14

申请号：US16355168

申请日：2019-03-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mohamed Assem Ibrahim ,  Onur Kayiran ,  Yasuko Eckert ,  Gabriel H. Loh

IPC: G06F12/0802 ,  G06F12/084 ,  G06F12/0846

Abstract: A method of dynamic cache configuration includes determining, for a first clustering configuration, whether a current cache miss rate exceeds a miss rate threshold. The first clustering configuration includes a plurality of graphics processing unit (GPU) compute units clustered into a first plurality of compute unit clusters. The method further includes clustering, based on the current cache miss rate exceeding the miss rate threshold, the plurality of GPU compute units into a second clustering configuration having a second plurality of compute unit clusters fewer than the first plurality of compute unit clusters.

公开(公告)号：US20220179741A1

公开(公告)日：2022-06-09

申请号：US17116952

申请日：2020-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Ross V. La Fetra

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/45

Abstract: A memory module includes logic elements that are configurable to a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode data such that any errors can be later identified and corrected. The approach allows a memory module or computing device to be configured to a specific ECC implementation without requiring requests to be sent back and forth between a host.

公开(公告)号：US20220171635A1

公开(公告)日：2022-06-02

申请号：US17673647

申请日：2022-02-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Steven Tony Tye ,  Brian Laird Sumner ,  Konstantin Zhuravlyov

IPC: G06F9/445 ,  G06F8/76

Abstract: Described herein are techniques for executing a heterogeneous code object executable. According to the techniques, a loader identifies a first memory appropriate for loading a first architecture-specific portion of the heterogeneous code object executable, wherein the first architecture specific portion includes instructions for a first architecture, identifies a second memory appropriate for loading a second architecture-specific portion of the heterogeneous code object executable, wherein the second architecture specific portion includes instructions for a second architecture that is different than the first architecture, loads the first architecture-specific portion into the first memory and the second architecture-specific portion into the second memory, and performs relocations on the first architecture-specific portion and on the second architecture-specific portion.