公开(公告)号：US11296653B2

公开(公告)日：2022-04-05

申请号：US17161855

申请日：2021-01-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud Gamet ,  Philippe Le Fevre

IPC: H03B5/36 ,  H03B5/14 ,  H03B5/32 ,  H03L1/02 ,  G01K7/32

Abstract: A shared pair of input/output cells configured to be able to be connected to a first external resonator or a second external resonator. A first oscillator and a second oscillator are coupled to the shared pair input/output cells by a switching circuit. The switching circuit is configured to be able to connect either the first oscillator or the second oscillator to the pair of input/output cells.

公开(公告)号：US11275589B2

公开(公告)日：2022-03-15

申请号：US16573299

申请日：2019-09-17

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Sebastien Metzger ,  Silvia Brini

IPC: G06F9/38 ,  G06F9/48 ,  G06F12/084 ,  G06F13/16

Abstract: A processor interacts with a memory set including a cache memory, a first memory storing at least a first piece of information in a first information group, and a second memory storing at least a second piece of information in a second information group. In response to a first cache miss and following a first request from the processor for the first piece of information, the first piece of information obtained from the first memory is supplied to the processor. After a second request from the processor for the second piece of information, the second piece of information obtained from the second memory is supplied to the processor, even if the first information group is currently being transferred from the first memory for loading into the cache memory.

公开(公告)号：US11271075B2

公开(公告)日：2022-03-08

申请号：US16802871

申请日：2020-02-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L21/00 ,  H01L49/02 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.

公开(公告)号：US11269986B2

公开(公告)日：2022-03-08

申请号：US16660243

申请日：2019-10-22

Applicant: STMicroelectronics (Grand Ouest) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Vincent Berthelot ,  Layachi Daineche

IPC: G06F21/00 ,  G06F21/44

Abstract: A memory stores a program to be executed by a microprocessor. The program includes a first program part and a second program part. An authenticator is configured to authenticate the program and includes a module that is external to the microprocessor and configured to authenticate said first program part when the microprocessor is inactive. The authenticator further activates the microprocessor to execute the first program part and authenticate said second program part using instructions of the first program part if the module has authenticated the first program part. The microprocessor then executes the second program part if the microprocessor has authenticated said second program part.

公开(公告)号：US20220066524A1

公开(公告)日：2022-03-03

申请号：US17396070

申请日：2021-08-06

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Herve CASSAGNES ,  Cyril MOULIN ,  Jean-Michel GRIL-MAFFRE

IPC: G06F1/24 ,  H03K17/22 ,  H03K19/17736

Abstract: Integrated circuit, method for resetting and computer program product. The integrated circuit comprises a first portion and a second portion. The first portion comprises a reset input configured to receive a reset signal, an activation module connected to the reset input. The activation module is configured to activate the second portion upon reception of the reset signal. The first portion comprises an emissions module configured to emit a replicated reset signal. The second portion can be selectively activated or deactivated. The second portion comprises a reset input configured to receive the replicated reset signal of the emissions module, a determination module configured to determine that an elapsed time starting from the activation of the second portion of the circuit oversteps a threshold.

公开(公告)号：US11250930B2

公开(公告)日：2022-02-15

申请号：US16709019

申请日：2019-12-10

Applicant: STMicroelectronics SA ,  STMicroelectronics (Rousset) SAS

Inventor： Stephane Denorme ,  Philippe Candelier ,  Joel Damiens ,  Fabrice Marinet

IPC: G11C17/00 ,  G11C29/52 ,  G11C17/12

Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.

公开(公告)号：US11238944B2

公开(公告)日：2022-02-01

申请号：US16824268

申请日：2020-03-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Chama Ameziane El Hassani

IPC: G11C16/32 ,  G11C16/10

Abstract: A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.

公开(公告)号：US20210408374A1

公开(公告)日：2021-12-30

申请号：US17362670

申请日：2021-06-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe BOIVIN

IPC: H01L45/00 ,  H01L27/24

Abstract: Memory devices and methods of manufacturing such devices are provided herein. In at least one embodiment, a memory device includes a plurality of phase-change memory cells. An electrically-insulating layer covers lateral walls of each of the phase-change memory cells, and a thermally-insulating material is disposed on the electrically-insulating layer and covers the lateral walls of the phase-change memory cells.

公开(公告)号：US11211428B2

公开(公告)日：2021-12-28

申请号：US16375557

申请日：2019-04-04

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin

IPC: H01L27/24 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/10 ,  H01L45/00

Abstract: The disclosure relates to integrated circuits including one or more rows of transistors and methods of forming rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a first semiconductor layer having a plurality of first conduction regions, a second semiconductor layer having a second conduction region, a common base between the first semiconductor layer and the second semiconductor layer, and a plurality of insulator walls extending in a first direction. The first conduction regions are separated from one another by the insulator walls. The integrated circuit further includes an insulating trench extending in a second direction and in contact with each of the bipolar transistors of the row of bipolar transistors. A conductive layer is coupled to the base, and the conductive layer extends through the insulator walls and extends at least partially into the insulating trench.

公开(公告)号：US20210377058A1

公开(公告)日：2021-12-02

申请号：US17329609

申请日：2021-05-25

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Benoit Froment ,  Jean-Marc Voisin

IPC: H04L9/32 ,  H03K19/003

Abstract: An integrated physical unclonable function device includes at least one reference capacitor and a number of comparison capacitors. A capacitance determination circuit operates to determine a capacitance of the at least one reference capacitor and a capacitance of each comparison capacitor. The determined capacitances of the comparison capacitors are then compared to the determined capacitance of the reference capacitor by a comparison circuit. A digital word is then generated with bit values indicative of a result of the comparisons made by the comparison circuit.