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公开(公告)号：US10552365B2
公开(公告)日：2020-02-04
申请号：US15902473
申请日：2018-02-22
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Chama Ameziane El Hassani
Abstract: In some embodiments, a buffer stage device includes a data input for receiving a data signal, a clock input for receiving a clock signal, a data output and a processor that is configured to deliver, to the data output, the data from the data signal in synchronism with clock cycles of the clock signal. The processor includes a first buffer module configured to deliver, to the data output, each datum in synchronism with a first edge of the clock signal and during a first half of a clock cycle, and a second buffer module configured to hold the datum at the data output during the second half of the clock cycle.
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2.发明申请公开(公告)号：US20200321063A1
公开(公告)日：2020-10-08
申请号：US16824268
申请日：2020-03-19
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Chama Ameziane El Hassani
Abstract: A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.
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公开(公告)号：US10558609B2
公开(公告)日：2020-02-11
申请号：US16204660
申请日：2018-11-29
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Chama Ameziane El Hassani
Abstract: In an embodiment, an electronic device for filtering an incoming digital signal includes several elementary filtering modules that include an elementary input configured to receive an incident elementary signal extracted from an incoming signal, an elementary output, and a dedicated capacitive circuit. The device further includes a resistive circuit common to all the elementary filtering modules and configured for cooperating with the capacitive circuit of each elementary filtering module in such a manner as to filter, on the respective elementary output, pulses of the incident elementary signal having a first voltage level and a duration less than a time constant and to deliver a filtered elementary signal on the elementary output.
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Patent Agency Ranking
公开(公告)号：US20190188179A1
公开(公告)日：2019-06-20
申请号：US16204660
申请日：2018-11-29
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Chama Ameziane El Hassani
IPC: G06F13/42
CPC classification number: G06F13/4282 , G06F2213/0016 , H03K5/1252
Abstract: In an embodiment, an electronic device for filtering an incoming digital signal includes several elementary filtering modules that include an elementary input configured to receive an incident elementary signal extracted from an incoming signal, an elementary output, and a dedicated capacitive circuit. The device further includes a resistive circuit common to all the elementary filtering modules and configured for cooperating with the capacitive circuit of each elementary filtering module in such a manner as to filter, on the respective elementary output, pulses of the incident elementary signal having a first voltage level and a duration less than a time constant and to deliver a filtered elementary signal on the elementary output.
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公开(公告)号：US20180322086A1
公开(公告)日：2018-11-08
申请号：US15902473
申请日：2018-02-22
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Chama Ameziane El Hassani
Abstract: In some embodiments, a buffer stage device includes a data input for receiving a data signal, a clock input for receiving a clock signal, a data output and a processor that is configured to deliver, to the data output, the data from the data signal in synchronism with clock cycles of the clock signal. The processor includes a first buffer module configured to deliver, to the data output, each datum in synchronism with a first edge of the clock signal and during a first half of a clock cycle, and a second buffer module configured to hold the datum at the data output during the second half of the clock cycle.
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公开(公告)号：US11670385B2
公开(公告)日：2023-06-06
申请号：US17558123
申请日：2021-12-21
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Chama Ameziane El Hassani
Abstract: A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.
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公开(公告)号：US20220115077A1
公开(公告)日：2022-04-14
申请号：US17558123
申请日：2021-12-21
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Chama Ameziane El Hassani
Abstract: A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.
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公开(公告)号：US11238944B2
公开(公告)日：2022-02-01
申请号：US16824268
申请日：2020-03-19
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Chama Ameziane El Hassani
Abstract: A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.
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