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公开(公告)号：US20210384257A1
公开(公告)日：2021-12-09
申请号：US17409612
申请日：2021-08-23
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Philippe BOIVIN
Abstract: The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.
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公开(公告)号：US20210280779A1
公开(公告)日：2021-09-09
申请号：US17328917
申请日：2021-05-24
Inventor： Philippe BOIVIN , Simon JEANNOT
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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公开(公告)号：US20190326510A1
公开(公告)日：2019-10-24
申请号：US16457855
申请日：2019-06-28
Inventor： Philippe BOIVIN , Simon JEANNOT
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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公开(公告)号：US20230240082A1
公开(公告)日：2023-07-27
申请号：US18193965
申请日：2023-03-31
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Philippe BOIVIN
CPC classification number: H10B63/24 , H10N70/021 , H10N70/063 , H10N70/231
Abstract: The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.
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公开(公告)号：US20160329490A1
公开(公告)日：2016-11-10
申请号：US15214054
申请日：2016-07-19
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Philippe BOIVIN , Julien DELALLEAU
IPC: H01L43/12 , H01L27/115 , H01L27/22 , H01L29/423 , H01L21/762 , H01L45/00 , H01L43/02 , H01L43/08 , H01L21/265 , H01L27/24 , H01L29/78
CPC classification number: H01L43/12 , H01L21/26513 , H01L21/76224 , H01L23/528 , H01L27/11507 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L29/42356 , H01L29/7827 , H01L43/02 , H01L43/08 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/16 , H01L2924/0002 , H01L2924/00
Abstract: The present disclosure relates to a method of making a memory on semiconductor substrate, comprising: at least one data line, at least one selection line, at least one reference line, at least one memory cell comprising a select transistor having a control gate connected to the selection line, a first conduction terminal connected to a variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, the select transistor comprising an embedded vertical gate produced in a trench formed in the substrate, and a channel region opposite a first face of the trench, between a first deep doped region and a second doped region on the surface of the substrate coupled to the variable impedance element.
Abstract translation: 本公开涉及一种在半导体衬底上制造存储器的方法，包括：至少一条数据线，至少一条选择线，至少一条参考线，至少一个存储单元，包括选择晶体管，其具有连接到 所述选择线，连接到可变阻抗元件的第一导电端子，所述选择晶体管和所述参考线耦合到所述数据线的所述可变阻抗元件，所述选择晶体管包括在形成在所述衬底中的沟槽中产生的嵌入垂直栅极，以及 与沟槽的第一面相对的沟道区，位于耦合到可变阻抗元件的衬底表面上的第一深掺杂区和第二掺杂区之间。
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Patent Agency Ranking
公开(公告)号：US20160013245A1
公开(公告)日：2016-01-14
申请号：US14737372
申请日：2015-06-11
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Philippe BOIVIN , Julien DELALLEAU
IPC: H01L27/24 , H01L43/08 , H01L43/12 , H01L45/00 , H01L29/78 , H01L23/528 , H01L29/423 , H01L21/265 , H01L21/762 , H01L27/115 , H01L43/02 , H01L27/22
CPC classification number: H01L43/12 , H01L21/26513 , H01L21/76224 , H01L23/528 , H01L27/11507 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L29/42356 , H01L29/7827 , H01L43/02 , H01L43/08 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/16 , H01L2924/0002 , H01L2924/00
Abstract: The present disclosure relates to a memory on semiconductor substrate, comprising: at least one data line, at least one selection line, at least one reference line, at least one memory cell comprising a select transistor having a control gate connected to the selection line, a first conduction terminal connected to a variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, the select transistor comprising an embedded vertical gate produced in a trench formed in the substrate, and a channel region opposite a first face of the trench, between a first deep doped region and a second doped region on the surface of the substrate coupled to the variable impedance element.
Abstract translation: 本公开涉及一种半导体衬底上的存储器，包括：至少一条数据线，至少一条选择线，至少一条参考线，至少一个存储单元，包括选择晶体管，该选择晶体管具有连接到选择线的控制栅极， 连接到可变阻抗元件的第一导电端子，所述选择晶体管和所述参考线耦合到所述数据线的所述可变阻抗元件，所述选择晶体管包括在形成于所述衬底中的沟槽中产生的嵌入垂直栅极和与所述衬底相对的沟道区域 沟槽的第一面，位于耦合到可变阻抗元件的衬底的表面上的第一深掺杂区域和第二掺杂区域之间。
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公开(公告)号：US20240276894A1
公开(公告)日：2024-08-15
申请号：US18646334
申请日：2024-04-25
Inventor： Philippe BOIVIN , Roberto SIMOLA , Yohann MOUSTAPHA-RABAULT
CPC classification number: H10N70/231 , H10B63/80 , H10N70/021 , H10N70/063 , H10N70/066 , H10N70/068 , H10N70/882 , H10N70/883
Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.
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公开(公告)号：US20240081160A1
公开(公告)日：2024-03-07
申请号：US18506383
申请日：2023-11-10
Inventor： Philippe BOIVIN , Simon JEANNOT
CPC classification number: H10N70/231 , H10B63/30 , H10B63/80 , H10N70/011 , H10N70/061 , H10N70/253 , H10N70/823 , H10N70/826 , H10N70/8265 , H10N70/8413 , H10N70/8828 , G11C13/0004
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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公开(公告)号：US20220130904A1
公开(公告)日：2022-04-28
申请号：US17507624
申请日：2021-10-21
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Philippe BOIVIN
Abstract: The present description concerns a method of forming a track in a first layer, including a) forming a cavity in the first layer; b) totally filling the cavity with a first material; and c) partially removing the first material from the upper portion of the cavity, to form the track made of the first material.
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公开(公告)号：US20220020816A1
公开(公告)日：2022-01-20
申请号：US17489425
申请日：2021-09-29
Inventor： Philippe BOIVIN , Jean Jacques FAGOT , Emmanuel PETITPREZ , Emeline SOUCHIER , Olivier WEBER
Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.
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