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公开(公告)号：US11997295B2
公开(公告)日：2024-05-28
申请号：US17428302
申请日：2021-05-28
Inventor： Jinfeng Liu
IPC: H04N19/186 , H04N19/182
CPC classification number: H04N19/186 , H04N19/182
Abstract: An image compression method includes: obtaining a grayscale pixel information of an original image, wherein the grayscale pixel information comprises a plurality of sub-grayscale pixel information; scanning the plurality of sub-grayscale pixel information according to a preset first scanning sequence to obtain a first target grayscale pixel information; dividing the first target grayscale pixel information into a plurality of first grayscale areas according to a preset first grayscale difference threshold to generate a first area information; and compressing the sub-grayscale pixel information of each first grayscale area according to the first minimum grayscale pixel value, the first area label, and the plurality of sub-grayscale pixel information, to obtain a first compressed data of the original image. An image compression device, a computer device, and a computer readable storage medium are also provided.
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公开(公告)号：US11995274B2
公开(公告)日：2024-05-28
申请号：US17822794
申请日：2022-08-28
Inventor： Xianjin Ge
CPC classification number: G06F3/044 , G06F3/0412 , G06F2203/04103 , G06F2203/04107
Abstract: The present invention provides a mask, a display panel, and a method for manufacturing thereof. The display panel includes a display area and a peripheral area surrounding the display area, and the peripheral area comprises a wiring area and a bonding area. The wiring area is provided with a first ground wiring. In the present invention, the first ground wiring is routed through a double-layer or multi-layer metal wiring, and an electrostatic discharge (ESD) protection effect can be achieved in the use of a finished product.
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公开(公告)号：US20240170955A1
公开(公告)日：2024-05-23
申请号：US17603073
申请日：2021-07-29
Inventor： Haoran LI
Abstract: A current limiting circuit includes a first voltage terminal, a second voltage terminal, a first transistor and a current limiting module. The first transistor includes an input terminal and an output terminal of the first transistor that are connected in series on a path formed by the first voltage terminal and the second voltage terminal. The current limiting module is electrically connected to a control terminal of the first transistor. The current limiting module is configured to output a control signal to the control terminal of the first transistor for controlling a state of the first transistor so that a current limiting value of the current limiting circuit is adjustable.
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公开(公告)号：US20240170465A1
公开(公告)日：2024-05-23
申请号：US17755530
申请日：2022-04-15
Inventor： Hejing Sun
CPC classification number: H01L25/167 , H01L24/32 , H01L25/162 , H01L2224/32052 , H01L2224/32225 , H01L2924/1426
Abstract: A splicing display panel is provided. In the present application, at least two light-emitting diode (LED) substrates are disposed on a driving substrate. The driving substrate includes a first conductive pad and a power signal line disposed on a first base. In each LED substrate, a connecting line layer is disposed on a second base and is electrically connected to the power signal line, and LED elements are disposed on the second base, wherein a first electrode of the LED element is electrically connected to the connecting line layer, and a second electrode of the LED element is electrically connected to the first conductive pad.
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公开(公告)号：US20240168692A1
公开(公告)日：2024-05-23
申请号：US17755521
申请日：2022-03-10
Inventor： Feng Zheng
CPC classification number: G06F3/1446 , G06F3/147
Abstract: Disclosed are a display module and a display device. The display module includes at least two display panels that are spliced; The display module further includes a groove disposed between two adjacent display panels and a light guiding portion disposed in the groove. The light guiding portion includes a light-incident surface near a bottom of the groove and a light-exiting surface away from the bottom of the groove.
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Patent Agency Ranking
公开(公告)号：US20240162400A1
公开(公告)日：2024-05-16
申请号：US17772772
申请日：2022-04-22
Inventor： Bin ZHAO , Juncheng XIAO , Xiaodan LIN
IPC: H01L33/62 , H01L25/075 , H01L25/16 , H01L27/12
CPC classification number: H01L33/62 , H01L25/0753 , H01L25/167 , H01L27/1244 , H01L2933/0016 , H01L2933/0066
Abstract: The present application provides a manufacturing method of an array substrate, an array substrate, and a display panel. The manufacturing method of the array substrate includes providing a base substrate; forming a conductive layer and a photoresist layer on the base substrate; patterning the photoresist layer and the conductive layer to form a conductive area and an electroplating area electrically connected to each other; removing the photoresist layer; forming an electroplating layer; and disconnecting the electroplating area from the conductive area. In the present application, the photoresist layer has a less thickness to reduce manufacturing costs of the array substrate.
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公开(公告)号：US20240162237A1
公开(公告)日：2024-05-16
申请号：US17778853
申请日：2022-05-17
Applicant: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. , HUIZHOU CHINA STAR OPTOELECTRONICS DISPLAY CO., LTD.
Inventor： Hui LI
IPC: H01L27/12 , H01L25/075 , H01L25/16 , H01L33/62
CPC classification number: H01L27/124 , H01L25/0753 , H01L25/167 , H01L33/62
Abstract: The embodiments of present the application disclose a display panel. The display panel includes a substrate disposed with a plurality of scanning lines and a plurality of data lines. A light-emitting component includes three scanning lines and two light-emitting units, and a light-emitting unit includes a plurality of sub light-emitting pixels. A number of the data lines is less than a number of the sub light-emitting pixels in the light-emitting unit, and a product of the number of the data lines and the number of the scanning lines is greater than or equal to the number of the sub light-emitting pixels. By electrically connecting the two light-emitting units with the three scanning lines, a load of the data lines is reduced and display effects are improved.
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公开(公告)号：US20240161711A1
公开(公告)日：2024-05-16
申请号：US17756663
申请日：2022-04-19
Inventor： Zhaoxian Zhong
IPC: G09G3/36 , G09G3/3266
CPC classification number: G09G3/3677 , G09G3/3266 , G09G2310/08
Abstract: The present disclosure relates to a circuit and a method for conditioning a clock signal, display panel, and display device. The circuit includes a signal conversion circuit and a delay processing circuit; when a voltage amplitude of the converted electrical signal falls within a turn-on threshold range, the delay processing circuit receives the N-th clock signal transmitted from the N-th clock signal output terminal, and performs delay processing on the N-th clock signal, so as to avoid occurrence of GOA-stage transfer abnormality when one of the plurality of CK clock signals is in an abnormal condition that no signal is output.
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公开(公告)号：US11984456B2
公开(公告)日：2024-05-14
申请号：US17600406
申请日：2021-08-17
Inventor： Ling Zhao , Weimin Chang , Juncheng Xiao
CPC classification number: H01L27/1244 , H01L27/1225 , H01L27/1262 , H01L27/127
Abstract: The present invention provides an array base plate and a manufacturing method therefor. The array base plate includes a substrate base plate layer, a first trace layer, an insulating layer, and a stress balance layer. The first trace layer includes a first trace. An edge of the stress balance layer is aligned to an edge of the substrate base plate layer. The stress balance layer has a bending stress in a direction opposite to a direction of the first trace and a curvature less than 1.2 mm/m.
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440.发明授权公开(公告)号：US11984073B2
公开(公告)日：2024-05-14
申请号：US16972038
申请日：2020-10-28
Inventor： Yan Li
IPC: G09G3/3233 , G09G3/3258
CPC classification number: G09G3/3233 , G09G3/3258 , G09G2320/0204 , G09G2320/0233
Abstract: A partitioned display structure includes a plurality of direct current (DC) voltage electrodes, each of the DC voltage electrodes is connected to a plurality of light-emitting units; a plurality of input voltage sources, the input voltage sources are connected to the DC voltage electrodes in a one-to-one manner, and are configured to transmit input signals to the plurality of light-emitting units for emitting light for displaying images; and a plurality of switches. Each of the switches is connected between two adjacent DC voltage electrodes to control a connection between the two adjacent DC voltage electrodes, the plurality of DC voltage electrodes are connected with each other in response to the plurality of switches in a turned-on state, and the plurality of DC voltage electrodes are insulated from each other in response to the plurality of switches in a turned-off state.
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