公开(公告)号：US20250028344A1

公开(公告)日：2025-01-23

申请号：US18770761

申请日：2024-07-12

Applicant: STMicroelectronics International N.V.

Inventor： Alessandra FARINA ,  Roberto Pio BAORDA ,  Stefano RAMORINI

IPC: G05F1/575 ,  G05F1/565

Abstract: An LDO regulator has a pass device arranged between an input node and an output node. The pass device is controlled at a control node by an error amplifier. A first current generator sources compensation current to the control node, a cascode device is arranged between the control node and a compensation node, and a second current generator sinks compensation current from the compensation node. A compensation capacitor is arranged between the output and compensation nodes. Load current through the pass device is sensed to generate a feedback current at a first feedback node. An input branch of a current mirror receives the feedback current. A filtering circuit is coupled between a control terminal of the input branch and a second feedback node. Output branches of the current mirror sink and source additional compensation current from the compensation node and the control node, respectively, proportional to the feedback current.

公开(公告)号：US20250027985A1

公开(公告)日：2025-01-23

申请号：US18752038

申请日：2024-06-24

Applicant: STMicroelectronics International N.V.

Inventor： Emanuele Moretti ,  Mauro Foppiani

IPC: G01R31/27 ,  G01R31/00 ,  G01R31/26 ,  G01R31/30 ,  G01R31/52

Abstract: A test circuit includes a set of electronic switches having a current path between a first node and a ground node, where each electronic switch has a respective control node. A set of coupling channels have one end coupled to a common test node and other ends coupled to the respective control nodes of electronic switches. A stress voltage supply source is coupled to the common test node. A set of comparator circuits includes comparator circuits having a first input node coupled, via sensing circuitry, to the control node of respective electronic switches in the set of electronic switches and having second nodes coupled to a threshold voltage node. A method of operating the test circuit is also disclosed.

公开(公告)号：US20250027970A1

公开(公告)日：2025-01-23

申请号：US18353678

申请日：2023-07-17

Applicant: STMicroelectronics International N.V.

Inventor： Stefano Paolo Rivolta ,  Federico Rizzardini ,  Lorenzo Bracco ,  Marco Bianco ,  Tae-gil Kang

IPC: G01P15/08

Abstract: According to an embodiment, a sensor including a machine learning core (MLC) and a finite state machine (FSM) circuit for detecting a shock event is provided. The MLC continuously calculates a value based on the change in velocity. The FSM circuit compares the value to a first threshold and generates a first interrupt if it is greater than the first threshold. The FSM circuit then compares the value to a second threshold less than the first threshold and generates a second interrupt if it is less than or equal to the second threshold after the first interrupt. The MLC calculates a maximum value between the first and second interrupts and stores it in a register, which is read by an application processor of a host device after receiving the second interrupt. The maximum acceleration norm value is reset after a delay after the second interrupt is generated.

公开(公告)号：US20250022509A1

公开(公告)日：2025-01-16

申请号：US18769493

申请日：2024-07-11

Applicant: STMicroelectronics International N.V.

Inventor： Francesco TOMAIUOLO ,  Marco RUTA ,  Michelangelo PISASALE ,  Marion Helne GRIMAL ,  Luigi BUONO ,  Antonino CONTE ,  Diego DE COSTANTINI ,  Marco Eugenio GIBILARO

IPC: G11C13/00

Abstract: A Phase Change Memory (PCM) device includes sets of cells in which a binary logic level is written by a write operation. Each cell is included in a respective set of cells in the sets of cells. The write operation includes: performing write verify operations on the cells to identify an actual logic level stored in the cells; checking if the identified actual logic level matches a certain the binary logic level; in response to the checking determining that in at least one cell the actual logic level fails to match the binary logic level, correcting the actual logic level to match the binary logic level by performing: a set write operation in case the binary logic level is a high logic level, or a reset write operation in case the binary logic level is a low logic level.

公开(公告)号：US20250020779A1

公开(公告)日：2025-01-16

申请号：US18350406

申请日：2023-07-11

Applicant: STMicroelectronics International N.V.

Inventor： Dominique Nuyts ,  Patrick Laurent

IPC: G01S7/481 ,  G01S17/08

Abstract: An electronic device that includes: a substrate including a first contact pad; a cap including a front surface, the cap being attached to a surface of the substrate, the front surface including a first recess and a second recess within the first recess, the cap including a first leadframe embedded within the cap; a first device mounted over the cap and within the second recess; and an optical lens mounted over the cap and the first device, where a first end of the first leadframe is extended out of the cap and electrically connected to the first contact pad, and where a second end of the first leadframe is extended out of the cap at the front surface and electrically connected to the first device.

公开(公告)号：US20250020710A1

公开(公告)日：2025-01-16

申请号：US18349791

申请日：2023-07-10

Applicant: STMicroelectronics International N.V.

Inventor： Francesco Rundo ,  Carmelo Pino ,  Michele Calabretta ,  Alessandro Sitta ,  Angelo Alberto Messina ,  Salvatore Coffa

IPC: G01R31/26

Abstract: A method for monitoring voltage drift includes measuring a voltage across a diode of a power device, providing the measured voltage as an input to a controller, the controller being configured to run a transformer-based model, and forecasting a range of expected future values of the voltage across the diode of the power device with the transformer-based model. The transformer-based model may include a temporal fusion transformer with a temporal convolutional neural network and an adversarial compensation model with a backpropagation algorithm.

公开(公告)号：US20250006724A1

公开(公告)日：2025-01-02

申请号：US18215899

申请日：2023-06-29

Applicant: STMicroelectronics International N.V.

Inventor： Leonardo DI BICCARI

IPC: H01L27/02

Abstract: A two terminal semiconductor controlled rectifier (SCR) device has an anode terminal coupled to a first node and a cathode terminal coupled to a second node. Neither of the cathode gate or anode gate of the SCR device are connected to a triggering circuit for controlling turn on of the SCR device. The SCR device has an avalanche breakdown voltage for turn on, where that avalanche breakdown voltage is set by a breakdown avalanche of a PN junction of the SCR device. A circuit path includes a series connected chain of M Zener diodes with a blocking diode that are coupled between the first node and the second node. The circuit path has an activation voltage for turn on, where that activation voltage is dependent on N times a Zener diode reverse breakdown voltage. The activation voltage is less than the avalanche breakdown voltage.

公开(公告)号：US20250004785A1

公开(公告)日：2025-01-02

申请号：US18742726

申请日：2024-06-13

Applicant: STMicroelectronics International N.V.

Inventor： Jawad BENHAMMADI

IPC: G06F9/4401

Abstract: The present description concerns a method of selection of boot programs, each contained in two separate storage memories of a microprocessor wherein an option register read first during a resetting of the microprocessor conditions the selection of one of the boot programs.

公开(公告)号：US20250004067A1

公开(公告)日：2025-01-02

申请号：US18677834

申请日：2024-05-29

Applicant: STMicroelectronics International N.V.

Inventor： Philippe Bienvenu ,  Antonio Calandra ,  Julia Castellan

IPC: G01R31/40

Abstract: The present disclosure relates to a device for measuring a power current supplied by a main power FET. The device includes a current measurement power FET coupled with the main FET; first and second FETs, the gates of which are coupled with each other, the first FET is coupled with the current measurement FET, in which a source/drain terminal of the second FET is coupled with a source/drain terminal of the first FET, or a source/drain terminal of the second FET is coupled with a source/drain terminal of the main FET or to a voltage source or load external to the device, and source/drain terminals of the first and second FETs are coupled with each other.

公开(公告)号：US20250004063A1

公开(公告)日：2025-01-02

申请号：US18742574

申请日：2024-06-13

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Jiri RYBA ,  Vittorio D'ANGELO ,  Salvatore CANNAVACCIUOLO ,  Mario DI GUARDO ,  Piero COLETTA

IPC: G01R31/389 ,  G01R31/3835 ,  G01R31/392 ,  H02J7/00

Abstract: The present disclosure relates to an EIS measuring device comprising: an electrical energy storage circuit; an electronic circuit coupled to the electrical energy storage circuit and configured to be coupled to a battery whose impedance is to be measured by the EIS measuring device, a characterization circuit configured to measure an alternative current intended to circulate between the battery and the electronic circuit, and a voltage at terminals of the battery; wherein the electronic circuit is alternately configured in a first mode to pull out electrical energy of the battery and storing the electrical energy pulled-out from the battery in the electrical energy storage circuit, and in a second mode to pull out the stored electrical energy from the electrical energy storage circuit and to re-inject the electrical energy pulled-out from the electrical energy storage circuit in the battery.