公开(公告)号：US5309347A

公开(公告)日：1994-05-03

申请号：US947105

申请日：1992-09-18

Applicant: Alberto Poma ,  Vanni Poletto ,  Marco Morelli

Inventor： Alberto Poma ,  Vanni Poletto ,  Marco Morelli

IPC: H03K17/08 ,  H02M1/00 ,  H02M1/38 ,  H03K17/082 ,  H03K17/66 ,  H02M3/155

CPC classification number: H02M1/38 ,  H03K17/0826 ,  H03K17/663

Abstract: An H-bridge circuit which includes four power transistors (an npn pull-down and a pnp pull-up for each of the output terminals). Two control circuits are connected to drive these transistors in a complementary crossover configuration, so that each control circuit can turn on the pull-up transistor on one side of the load and the pull-down transistor on the opposite side of the load. Each of the power transistors is paralleled (base-to-base) by a smaller transistor which provides a scaled current output (proportional to that of the corresponding power transistor) to the opposite control circuit. The control circuit includes static current-thresholding disable logic, which prevents turn-on until the currents through the opposite power devices have declined to threshold levels. Thus, as long as either control circuit is driving one of the pull-up transistors into in the on-state, the other control circuit will not be able to turn on the pull-down transistor which is in series with the active pull-up transistor. This efficiently prevents any condition of unlimited crowbar current, without adding any excess delay or causing any high-impedance condition at the output.

Abstract translation: 一个H桥电路，包括四个功率晶体管（npn下拉和每个输出端子的pnp上拉）。 连接两个控制电路以以互补的交叉配置驱动这些晶体管，使得每个控制电路可以在负载的一侧上的上拉晶体管和负载的相对侧上的下拉晶体管导通。 每个功率晶体管由较小的晶体管并联（基极到基极），其提供与相对的控制电路成比例的电流输出（与对应的功率晶体管成比例）。 控制电路包括静态电流阈值禁用逻辑，其可以防止导通，直到通过相对的功率器件的电流已经下降到阈值电平。 因此，只要任一控制电路将上拉晶体管中的一个驱动到导通状态，则另一控制电路将不能接通与有源上拉串联的下拉晶体管 晶体管。 这有效地防止了无限制的撬棒电流的任何条件，而不会增加任何超出延迟或在输出端引起任何高阻抗条件。

公开(公告)号：US5276644A

公开(公告)日：1994-01-04

申请号：US791453

申请日：1991-11-13

Applicant: Luigi Pascucci ,  Marco Olivo

Inventor： Luigi Pascucci ,  Marco Olivo

IPC: G11C17/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28 ,  G11C7/00

CPC classification number: G11C7/14 ,  G11C16/28

Abstract: A non-volatile memory in which, during read operations, the sense amplifier's first input is connected not only to a selected non-programmed reference cell, but also to a current of a value one half the current that flows in a programmed cell; and the sense amplifier's second input is connected not only to a selected matrix cell to be read, but also to a current of a value one half the current that flows in a non-programmed cell.

Abstract translation: 一种非易失性存储器，其中在读取操作期间，读出放大器的第一输入不仅连接到所选择的非编程参考单元，而且还连接到在编程单元中流动的电流的一半的电流; 并且读出放大器的第二输入不仅连接到要读取的所选择的矩阵单元，而且还连接到在非编程单元中流动的电流的一半的电流。

公开(公告)号：US5258959A

公开(公告)日：1993-11-02

申请号：US810480

申请日：1991-12-19

Applicant: Marco Dallabora ,  Corrado Villa

Inventor： Marco Dallabora ,  Corrado Villa

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  G11C7/02

CPC classification number: G11C16/28

Abstract: A memory cell reading circuit has a reference cell bit line and a matrix cell bit line connected to a supply voltage through respective loads and are furthermore connected by normally-off equalization transistors which are enabled by a first clock signal. The bit lines are further connected by normally-off resistive equalization transistors whose resistance is significant in conducting conditions. The equalization transistors are enabled by a first clock signal and the resistive equalization transistors are enabled by a second clock signal which has a duration that extends longer than the first clock signal. The memory cell reading circuit decreases the "read" time required for a memory cell, such as an EPROM cell, as compared to reading circuits previously used.

公开(公告)号：US5220217A

公开(公告)日：1993-06-15

申请号：US812135

申请日：1991-12-18

Applicant: Flavio Scarra ,  Maurizio Gaibotti ,  Giampiero Trupia

Inventor： Flavio Scarra ,  Maurizio Gaibotti ,  Giampiero Trupia

IPC: G01R31/3183 ,  G01R31/317 ,  G01R31/3185 ,  H03K5/135

CPC classification number: G01R31/318552 ,  G01R31/31727 ,  H03K5/135

Abstract: The circuit comprises a first switching circuit which receives at an input a system clock normally provided for the operation of the integrated circuit and produces at an output a machine clock normally coincident with the system clock, circuitry for clamping the first switching circuit responsive to a firing signal of the serial operational analysis device determines which state the machine clock is clamped in and second switching circuit which receives at an input the system clock and is responsive to the firing signal to produce a scanning clock which repeats the system clock in an inverted or non-inverted manner according to the state in which the machine clock has been clamped.

公开(公告)号：US5200653A

公开(公告)日：1993-04-06

申请号：US718669

申请日：1991-06-21

Applicant: David Moloney ,  Gianfranco Vai ,  Maurizio Zuffada ,  Giorgio Betti

Inventor： David Moloney ,  Gianfranco Vai ,  Maurizio Zuffada ,  Giorgio Betti

IPC: H03K19/0175 ,  H03K19/094 ,  H03K19/0948

CPC classification number: H03K19/0948 ,  H03K19/09429

Abstract: The tristate output gate structure particularly for CMOS integrated circuits, comprises an enable terminal receiving an enable signal and an input terminal receiving an input signal, which connects, through signal switching means, an output terminal to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor through signal inverting means and to the gate terminal of a second N-channel transistor. The output terminal is electrically connected to the drain terminals of the first and second transistors. The first and second transistors electrically insulate the output terminal from the input terminal.

公开(公告)号：US5194821A

公开(公告)日：1993-03-16

申请号：US793628

申请日：1991-11-18

Applicant: Davide Brambilla ,  Guido Brasca ,  Edoardo Botti

Inventor： Davide Brambilla ,  Guido Brasca ,  Edoardo Botti

IPC: H03F1/02 ,  H03F3/20 ,  H03F3/30 ,  H03F3/68 ,  H03G3/30

CPC classification number: H03F1/0277 ,  H03F3/3081

Abstract: The amplifier comprises a first and a second amplifier block of opposite phase driven by a single input signal and having its outputs connected to the two terminals of a load. It also comprises circuit means to disable one of the said amplifier blocks when the absolute value of the input signal is less than a predetermined threshold level. A passive feedback system capable of maintaining the amplifier gain constant is located between the aforesaid terminals of the load and the inputs to the two amplifier blocks.

公开(公告)号：US5185649A

公开(公告)日：1993-02-09

申请号：US675558

申请日：1991-03-26

Applicant: Franco Bertotti ,  Paolo Ferrari

Inventor： Franco Bertotti ,  Paolo Ferrari

IPC: H01L27/06 ,  H01L21/331 ,  H01L27/02 ,  H01L29/73 ,  H01L29/732

CPC classification number: H01L27/0248

Abstract: A circuital arrangement which comprises a vertical PNP transistor with insulated collector, which has a P-type collector structure surrounded by an N-type well and forms a junction therewith. In order to prevent latch-ups of the parasite SCR which is formed by the structure of the vertical transistor with insulated collector without limiting the voltage which can be applied between the collector and the emitter thereof to values below the intrinsic breakdown ones, the circuital arrangement comprises an auxiliary PNP transistor the emitter whereof is short-circuited with the emitter of the vertical PNP transistor, the base whereof is connected to the base of the vertical PNP transistor and the collector whereof is connected to the N-type well, and operates as a switch which biases the N-type well at a voltage which is close to the voltage of the emitter of the vertical PNP transistor when the latter is saturated, reverse-biasing the collector/N-well junction, and opens when the vertical PNP transistor is off, limiting the voltage applied to the collector/N-well junction.

公开(公告)号：US5170133A

公开(公告)日：1992-12-08

申请号：US669898

申请日：1991-03-14

Applicant: Sergio Pernici

Inventor： Sergio Pernici

IPC: H03F3/187 ,  H03F3/26 ,  H03F3/45

CPC classification number: H03F3/265 ,  H03F2200/372

Abstract: The amplifier includes a pair of bipolar input transistors (Q1, Q2), each having a base adapted to receive a differential input signal, a collector and an emitter which is biased by a first fixed current source (M7, M8) of its own and a degeneration resistor (R) which connects the emitters of the two bipolar transistors. The collector of each bipolar transistor is also biased by a second fixed current source (M5, M6) with a smaller current than that of the first source, and the collectors of the two bipolar transistors are furthermore connected to the input terminals of respective MOS amplifier devices (M1, M2, M3, M4, R.sub.L). The amplifier can be made in BCD, BiCMOS or purely CMOS technology, in which case the bipolar transistors are obtained as lateral bipolar transistors.

公开(公告)号：US5168181A

公开(公告)日：1992-12-01

申请号：US705006

申请日：1991-05-23

Applicant: Antonella Baiocchi ,  Angelo Alzati ,  Aldo Novelli

Inventor： Antonella Baiocchi ,  Angelo Alzati ,  Aldo Novelli

IPC: H03K5/1254 ,  H03K5/1252

CPC classification number: H03K5/1252

Abstract: A spike filtering circuit for a logic signal comprises a signal transfer circuit formed by a first transfer gate followed by a pair of inverters, functionally connected in series between the input terminal and the output terminal of the circuit and a second transfer gate connected between the output terminal and the input node of the first of said two inverters. The two transfer gates are driven in phase opposition to each other by means of a pair of control signals in phase opposition to each other which are generated by a control circuit functioning in a feedback mode. Basically the control circuit is formed by an exclusive-OR gate having two inputs connected to the output terminal of the circuit directly and through a delay network, respectively. Through an output node of the exclusive-OR gate is produced a first control signal from which the pair of control signals in phase opposition to each other are derived by means of inverting stages. The delay network introduces a delay after a transition of the signal on the output terminal of the circuit has occurred during which said first transfer gate is momentarily disabled and said second transfer gate is enabled in order to maintain on the output terminal the state reached with the first transition for a period of time sufficiently long to allow the decay of spikes which may be been generated by said transition of the logic signal. By employing a NAND gate and an inverter connected in cascade to the output of said exclusive-OR gate, the filtering circuit may be initialled by applying an enabling signal to a second input of said NAND gate.

公开(公告)号：US5160854A

公开(公告)日：1992-11-03

申请号：US734911

申请日：1991-07-24

Applicant: Fabrizio Martignoni ,  Claudio Diazzi ,  Albino Pidutti ,  Fabio Vio

Inventor： Fabrizio Martignoni ,  Claudio Diazzi ,  Albino Pidutti ,  Fabio Vio

IPC: H03K17/04 ,  H03K17/0412 ,  H03K17/06 ,  H03K17/687 ,  H03K19/0185

CPC classification number: H03K17/06 ,  H03K17/04123 ,  H03K17/063

Abstract: A level shifter, particularly suited for driving power stages for supplying power to integrated circuits, includes a DMOS transistor (40) which is driven by a digital signal source (42) and has a load resistor (44) as its drain load. A shifted output signal develops at the ends of said load resistor. The drain (V1) of the DMOS transistor is connected to the input of an inverter (46), while a Zener diode (54) and a second transistor (52) are connected in parallel with the load resistor (44), the gate of the second transistor (52) being driven by the output of the inverter (46). The output of the inverter (46) can be connected to the input of a drive stage (48), the output of which drives a power stage (50) for supplying power to an integrated circuit.