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    Cross-Component Optimizing Compiler Systems
    41.
    发明申请
    Cross-Component Optimizing Compiler Systems 有权

    公开(公告)号：US20250004731A1

    公开(公告)日：2025-01-02

    申请号：US18214748

    申请日：2023-06-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Hashim Sharif ,  Johnathan Robert Alsop

    IPC: G06F8/41

    Abstract: Cross-component optimizing compiler systems are described. In accordance with the described techniques, machine learning models receive components of source code to be compiled. The machine learning models generate component prediction functions for the components of the source code. A tuning engine selects parameters for the components of the source code based on the component prediction functions. Domain-specific language compilers compile the source code based on the selected parameters.

    Mitigation Of Undershoot And Overshoot On A Power Rail
    43.
    发明申请
    Mitigation Of Undershoot And Overshoot On A Power Rail 有权

    公开(公告)号：US20250004516A1

    公开(公告)日：2025-01-02

    申请号：US18346070

    申请日：2023-06-30

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Josip Popovic ,  Anshuman Mittal ,  Kellie Marks

    IPC: G06F1/26

    Abstract: An apparatus and method for efficiently managing voltage droop among replicated compute circuits of an integrated circuit. In various implementations, an integrated circuit includes multiple, replicated compute circuits, each with the circuitry of multiple lanes of execution. Control circuitry of the integrated circuit identifies, early in execution pipelines, groups of instructions to be executed by a corresponding compute circuit, and generates a total power consumption estimate for the groups. The control circuitry maintains N previous total power consumption estimates, and stores the N power consumption estimates in staging circuitry referred to as an “instruction history pipeline.” If any differences between total power consumption estimates of different stages of the instruction history pipeline exceeds a corresponding threshold, then the control circuitry reduces, late in the execution pipeline, the rate of instruction execution of computation lanes of a corresponding compute circuit.

    Systems and methods for restoring bus functionality
    45.
    发明授权
    Systems and methods for restoring bus functionality 有权

    公开(公告)号：US12181993B1

    公开(公告)日：2024-12-31

    申请号：US18078735

    申请日：2022-12-09

    Applicant: Advanced Micro Devices, Inc.

    Inventor： KaiFei Zhao ,  LiLi Chen ,  Wei Han

    IPC: G06F11/00 ,  G06F11/07 ,  G06F11/14 ,  G06F11/30

    Abstract: A disclosed method for restoring bus functionality includes detecting, by an automatic bus recovery block, that at least one target device on a bus pulls at least one line of the bus to a low level. The method also includes initiating, by the automatic bus recovery block, a timer to time a duration of the low level of the line. Additionally, the method includes detecting, by the automatic bus recovery block, that the duration of the low level of the line exceeds a predetermined time limit. Furthermore, the method includes alerting, by the automatic bus recovery block, a controller device on the bus that the duration of the low level exceeds the predetermined time limit to reset the line of the bus to a high level. Various other methods, systems, and computer-readable media are also disclosed.

    Systems and methods for enabling debugging
    46.
    发明授权
    Systems and methods for enabling debugging 有权

    公开(公告)号：US12181955B1

    公开(公告)日：2024-12-31

    申请号：US18087894

    申请日：2022-12-23

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Lu Lu ,  Dong Zhu ,  Gia Phan ,  James A. Ott ,  Nehal Patel ,  Zang SongGan

    IPC: G06F11/07 ,  G06F11/34 ,  G06F11/36

    Abstract: A computer-implemented method for enabling debugging can include receiving, at a peripheral device connected through an expansion socket to a base CPU platform, a scan dump instruction from a network computing device connected to the base CPU platform across a network connection and executing, by a System-on-Chip at the peripheral device in response to the scan dump instruction, a debugging procedure. The debugging procedure can include capturing a snapshot of memory of the peripheral device and transmitting the snapshot to the network computing device through memory addresses that have been assigned to memory-mapped input/output. Various other methods, systems, and computer-readable media are also disclosed.

    MULTIMODAL CONTEXTUALIZER FOR NON-PLAYER CHARACTER GENERATION AND CONFIGURATION
    48.
    发明申请
    MULTIMODAL CONTEXTUALIZER FOR NON-PLAYER CHARACTER GENERATION AND CONFIGURATION 有权

    公开(公告)号：US20240428494A1

    公开(公告)日：2024-12-26

    申请号：US18749032

    申请日：2024-06-20

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Karthik Mohan Kumar ,  Michael Mantor ,  Pedro Antonio Pena ,  Archana Ramalingam

    IPC: G06T13/40 ,  H04N19/124

    Abstract: Systems and techniques for generating and animating non-player characters (NPCs) within virtual digital environments are provided. Multimodal input data is received that comprises a plurality of input modalities for interaction with an NPC having a set of body features and a set of facial features. The multimodal input data is processed through one or more neural networks to generate animation sequences for both the body features and facial features of the NPC. Generating such animation sequences includes disentangling the multimodal input data to generate substantially disentangled latent representations, combining these representations with the multimodal input data, and using a large-language model (LLM) to generate speech data for the NPC. Further processing using reverse diffusion generates face vertex displacement data and joint trajectory data based on the combined representation and generated speech data. The face vertex displacement data, joint trajectory data, and speech data are used to produce an animated representation of the NPC, which is then provided to environment-specific adapters to animate the NPC within a virtual digital environment.

    Dynamic random-access memory (DRAM) phase training update
    50.
    发明授权
    Dynamic random-access memory (DRAM) phase training update 有权

    公开(公告)号：US12175102B2

    公开(公告)日：2024-12-24

    申请号：US18378893

    申请日：2023-10-11

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Scott P. Murphy ,  Huuhau M. Do

    IPC: G06F3/00 ,  G06F3/06

    Abstract: A phase training update circuit operates to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and determines a second number of errors in the transmission. Responsive to a difference between the first number of errors and the second number of errors, the phase training update circuits adjusts a center phase position for the bit lane transmit phase offset of the selected bit lane.

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