公开(公告)号：US20220374169A1

公开(公告)日：2022-11-24

申请号：US17398091

申请日：2021-08-10

Applicant: Microchip Technology Inc.

Inventor： Lorenzo Zuolo ,  Rino Micheloni

IPC: G06F3/06 ,  G06N3/08

Abstract: A method for meeting quality of service (QoS) requirements in a flash controller that includes one or more instruction queues and a neural network engine. A configuration file for a QoS neural network is loaded into the neural network engine. A current command is received at the instruction queue(s). Feature values corresponding to commands in the instruction queue(s) are identified and are loaded into the neural network engine. A neural network operation of the QoS neural network is performed using as input the identified feature values to predict latency of the current command. The predicted latency is compared to a first latency threshold. When the predicted latency exceeds the first latency threshold one or more of the commands in the instruction queue(s) are modified. The commands are not modified when the predicted latency does not exceed the latency threshold. A next command in the instruction queue(s) is then performed.

公开(公告)号：US20220342844A1

公开(公告)日：2022-10-27

申请号：US17701582

申请日：2022-03-22

Applicant: Microchip Technology Inc.

Inventor： Christopher I. W. NORRIE

IPC: G06F15/80

Abstract: In one implementation a vector processor unit having preload registers for at least some of vector length, vector constant, vector address, and vector stride. Each preload register has an input and an output. All the preload register inputs are coupled to receive a new vector parameters. Each of the preload registers' outputs are coupled to a first input of a respective multiplexor, and the second input of all the respective multiplexors are coupled to the new vector parameters.

公开(公告)号：US11424902B2

公开(公告)日：2022-08-23

申请号：US17242493

申请日：2021-04-28

Applicant: Microchip Technology Inc.

Inventor： Atanu Chattopadhyay ,  Andras de Koos

IPC: H04L7/00 ,  H04L43/0864

Abstract: System and method for synchronizing a plurality of nodes to a timing signal using a daisy-chain network having a forward transmission path and a reverse transmission path connected at a midpoint. Latency of the timing signal to the midpoint of the daisy-chain network is determined, a respective latency of the timing signal from the node to the midpoint of the daisy-chain network is determined, and a respective timing offset for each of the plurality of nodes is calculated. A local time-of-day counter at each of the plurality of nodes is adjusted based upon the respective timing offset of the node to synchronize the plurality of nodes to the timing signal.

公开(公告)号：US20220262434A1

公开(公告)日：2022-08-18

申请号：US17736563

申请日：2022-05-04

Applicant: Microchip Technology Inc.

Inventor： Victor Nguyen ,  Fethi Dhaoui ,  John L. McCollum ,  Fengliang Xue

IPC: G11C13/00 ,  H01L45/00

Abstract: A ReRAM memory array includes ReRAM memory cells and a select circuit having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on.

公开(公告)号：US11323123B2

公开(公告)日：2022-05-03

申请号：US16827691

申请日：2020-03-23

Applicant: Microchip Technology Inc.

Inventor： Mike Willingham

IPC: H03L7/099 ,  H03L7/081 ,  H03L7/10 ,  H03L7/197

Abstract: A circuit for correcting phase interpolator rollover integral non-linearity errors includes a rollover detector circuit for detecting when a rollover event of a phase interpolator has occurred, and a correction circuit that adds a signed predistortion correction to a VCO clock cycle phase fraction value when the rollover detector circuit has detected the interpolator rollover event.

公开(公告)号：US20220058488A1

公开(公告)日：2022-02-24

申请号：US17148200

申请日：2021-01-13

Applicant: Microchip Technology Inc.

Inventor： Lorenzo Zuolo ,  Rino Micheloni

IPC: G06N3/08 ,  G06N3/04

Abstract: A method includes storing configuration files of a Multi-Core Neural Network Inference (MCNNI) model having Independent Categorized-Core-Portions (ICCP's). Each ICCP corresponds to one of a plurality of categories for each parameter. A first plurality of weighting values on each row of the weighting matrix of the MCNNI model have a nonzero value and a second plurality of weighting values on each row having a value of zero. The configuration files are loaded into a neural network engine. The operation of the integrated circuit device is monitored to identify a usage value corresponding to each of the parameters. A single neural network operation is performed using the usage values as input to generate, at the output neurons of each ICCP, output values indicating an estimation of one or more variable. The output values of the ICCP that corresponds to the input usage values are identified and are sent as output.

公开(公告)号：US11257734B2

公开(公告)日：2022-02-22

申请号：US16816874

申请日：2020-03-12

Applicant: Microchip Technology Inc.

Inventor： Damian McCann

IPC: H01L23/367 ,  H01L23/373

Abstract: A thermal management package for a semiconductor device includes a high dielectric constant material substrate, a high thermal conductivity slug disposed in a first window in the high dielectric constant material substrate and held therein by a first bonding material, an outer substrate formed from a material having a low dielectric constant and having a second window formed therein, the high dielectric constant material substrate disposed in the second window in the low dielectric constant outer substrate and held therein by a second bonding material.

公开(公告)号：US20220034684A1

公开(公告)日：2022-02-03

申请号：US17075157

申请日：2020-10-20

Applicant: Microchip Technology Inc.

Inventor： Stephane Le Goff ,  Mathieu Sureau ,  Jebas Paul Daniel T ,  Naveen Cannankurichi ,  Subhasis Sasmal ,  Sunny Joel

IPC: G01D5/244 ,  G01B7/00 ,  G01D5/20

Abstract: A system and method for monitoring analog front-end (AFE) circuitry of an inductive position sensor. A redundant AFE channel is provided and alternatively utilized with a sine AFE channel or a cosine AFE channel of the AFE circuitry to obtain a voltage difference that may result in a detection angle error at the electronic control unit (ECU) of the inductive position sensor.

公开(公告)号：US20210373898A1

公开(公告)日：2021-12-02

申请号：US17075493

申请日：2020-10-20

Applicant: Microchip Technology Inc.

Inventor： Pierre Selwan

IPC: G06F9/38 ,  G06F13/20 ,  G06F9/52

Abstract: A system and method for monitoring processors operating in lockstep to detect mismatches in pending pipelined instructions being executed by the processors. A lockstep monitor implemented in hardware is provided to detect the mismatches in the pending pipelined instructions executing on the lockstep processors and to initiate an auto-recovery operation at the processors if a mismatch is detected.

公开(公告)号：US20210173993A1

公开(公告)日：2021-06-10

申请号：US17111218

申请日：2020-12-03

Applicant: Microchip Technology Inc.

Inventor： Madhusudan Raman ,  Nizar Abdallah ,  Julien G. Dunoyer

IPC: G06F30/343 ,  G06N3/08

Abstract: A method for integrated circuit design with delay verification includes storing configuration files for a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model. A user design is received, slew-rate feature values, net-delay feature values and cell-delay feature values are extracted from the user design, the configuration files are loaded to form inference cores, and operations of the slew-rate inference core are performed to calculate predicted slew-rate values that are sent to ML design tools. Operations of the net-delay inference core are performed to calculate predicted net-delay values that are sent to the ML design tools. Operations of the cell-delay inference core are performed to generate predicted cell-delay values that are sent to the ML design tools. The user design is iterated until a user design is obtained that is free of timing violations.