公开(公告)号：US20130140668A1

公开(公告)日：2013-06-06

申请号：US13312442

申请日：2011-12-06

Applicant: Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Mark E. Stidham ,  Robert M. Rassel

Inventor： Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Mark E. Stidham ,  Robert M. Rassel

IPC: H01L27/04 ,  H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/26506 ,  H01L21/823892 ,  H01L27/04 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0802 ,  H01L27/0811 ,  H01L27/0928

Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

Abstract translation: 衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率 用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。

公开(公告)号：US20120319229A1

公开(公告)日：2012-12-20

申请号：US13596410

申请日：2012-08-28

Applicant: Alan B. Botula ,  Beth Ann Rainey ,  Yun Shi

Inventor： Alan B. Botula ,  Beth Ann Rainey ,  Yun Shi

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L29/2003

Abstract: Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.

Abstract translation: 提供了在衬底中和在绝缘体上绝缘体（SOI）器件上的高压绝缘体（SOI）器件下面具有掺杂带的集成电路。 在一个实施例中，本发明提供一种集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：基板; 衬底上的掩埋氧化物（BOX）层; 以及位于BOX层顶部的半导体层; 在半导体层内串联连接的多个高压（HV）器件; 在所述衬底内并在所述多个HV器件中的第一个之下的掺杂带; 以及从半导体层和BOX层延伸到掺杂带的接触。

公开(公告)号：US08299547B2

公开(公告)日：2012-10-30

申请号：US12983439

申请日：2011-01-03

Applicant: Michel J. Abou-Khalil ,  Alan B. Botula ,  Alvin J. Joseph ,  Theodore J. Letavic ,  James A. Slinkman

Inventor： Michel J. Abou-Khalil ,  Alan B. Botula ,  Alvin J. Joseph ,  Theodore J. Letavic ,  James A. Slinkman

IPC: H01L21/336

CPC classification number: H01L29/7824 ,  G06F17/5063 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/785

Abstract: A lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) with a high drain-to-body breakdown voltage (Vb) incorporates gate structure extensions on opposing sides of a drain drift region. The extensions are tapered such that a distance between each extension and the drift region increases linearly from one end adjacent to the channel region to another end adjacent to the drain region. In one embodiment, these extensions can extend vertically through the isolation region that surrounds the LEDMOSFET. In another embodiment, the extensions can sit atop the isolation region. In either case, the extensions create a strong essentially uniform horizontal electric field profile within the drain drift. Also disclosed are a method for forming the LEDMOSFET with a specific Vb by defining the dimensions of the extensions and a program storage device for designing the LEDMOSFET to have a specific Vb.

Abstract translation: 具有高漏极对体击穿电压（Vb）的横向延伸漏极，金属氧化物半导体场效应晶体管（LEDMOSFET）在漏极漂移区域的相对侧上并入门结构延伸。 延伸部是锥形的，使得每个延伸部和漂移区域之间的距离从邻近通道区域的一端线性地增加到与漏极区域相邻的另一端部。 在一个实施例中，这些扩展可以垂直延伸通过围绕LEDMOSFET的隔离区域。 在另一个实施例中，扩展可以位于隔离区域的顶部。 在任一种情况下，扩展在漏极漂移内产生强大的基本均匀的水平电场分布。 还公开了通过限定扩展的尺寸来形成具有特定Vb的LEDMOSFET的方法以及用于将LEDMOSFET设计为具有特定Vb的程序存储装置。

公开(公告)号：US20120104496A1

公开(公告)日：2012-05-03

申请号：US13345871

申请日：2012-01-09

Applicant: Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

Inventor： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

IPC: H01L27/088 ,  G06F17/50

CPC classification number: H01L21/84 ,  H01L21/76264 ,  H01L27/1203

Abstract: At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.

Abstract translation: 至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。 浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。 所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。 感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。

公开(公告)号：US20120038024A1

公开(公告)日：2012-02-16

申请号：US12853532

申请日：2010-08-10

Applicant: Alan B. BOTULA ,  Dinh DANG ,  James S. DUNN ,  Alvin J. JOSEPH ,  Peter J. LINDGREN

Inventor： Alan B. BOTULA ,  Dinh DANG ,  James S. DUNN ,  Alvin J. JOSEPH ,  Peter J. LINDGREN

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/76289 ,  H01L27/0738 ,  H01L27/1203 ,  H01L29/0649

Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

Abstract translation: 绝缘体上硅（SOI）衬底中的低谐波射频（RF）开关及其制造方法。 一种方法包括通过绝缘体层形成至少一个沟槽。 所述至少一个沟槽与形成在所述绝缘体层上的有源区域中的器件相邻。 该方法还包括在绝缘体层之下的衬底中形成至少一个空腔，并从该至少一个沟槽横向延伸到该器件的下方。

公开(公告)号：US20110284961A1

公开(公告)日：2011-11-24

申请号：US13197414

申请日：2011-08-03

Applicant: Alan B. Botula ,  Alvin J. Joseph ,  Alan F. Norris ,  Robert M. Rassel ,  Yun Shi

Inventor： Alan B. Botula ,  Alvin J. Joseph ,  Alan F. Norris ,  Robert M. Rassel ,  Yun Shi

IPC: H01L29/786 ,  G06F17/50 ,  G06F11/22

CPC classification number: H01L29/7839 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/66659

Abstract: A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of a first conductivity type, which is the opposite of the second conductivity type, on one side of a dummy gate electrode and a Schottky barrier structure surrounded by the doped guard ring on the other side. A Schottky barrier region may be laterally surrounded by the dummy gate electrode and the doped guard ring. The doped guard ring includes an unmetallized portion of a gate-side second-conductivity-type-doped semiconductor region having a doping of a second conductivity type. A Schottky barrier region may be laterally surrounded by a doped guard ring including a gate-side doped semiconductor region and a STI-side doped semiconductor region. Design structures for the inventive Schottky barrier diode are also provided.

Abstract translation: 肖特基势垒二极管包括在绝缘体上半导体（SOI）衬底中具有第二导电类型掺杂的掺杂保护环。 肖特基势垒二极管还包括在虚拟栅极电极的一侧上具有与第二导电类型相反的第一导电类型的掺杂的第一导电型掺杂半导体区域，以及被包围的肖特基势垒结构 另一侧的掺杂保护环。 肖特基势垒区域可以被伪栅电极和掺杂保护环横向包围。 掺杂保护环包括具有第二导电类型的掺杂的栅极侧第二导电型掺杂半导体区域的未金属化部分。 肖特基势垒区域可以由包括栅极掺杂半导体区域和STI侧掺杂半导体区域的掺杂保护环横向包围。 还提供了用于本发明的肖特基势垒二极管的设计结构。

公开(公告)号：US08026131B2

公开(公告)日：2011-09-27

申请号：US12342488

申请日：2008-12-23

Applicant: Alan B. Botula ,  Edward J. Nowak ,  James A. Slinkman

Inventor： Alan B. Botula ,  Edward J. Nowak ,  James A. Slinkman

IPC: H01L21/00 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L21/76224 ,  H01L21/76251 ,  H01L27/1203

Abstract: First doped semiconductor regions having the same type doping as a bottom semiconductor layer and second doped semiconductor regions having an opposite type doping are formed directly underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. The first doped semiconductor regions and the second doped semiconductor regions are electrically grounded or forward-biased relative to the bottom semiconductor layer at a voltage that is insufficient to cause excessive current due to forward-biased injection of minority carriers into the bottom semiconductor layer, i.e., at a potential difference not exceeding 0.6 V to 0.8V. The electrical charges formed in an induced charge layer by the electrical signal in semiconductor devices on the top semiconductor layer are drained through electrical contacts connected to the first and second doped semiconductor regions, thereby reducing of harmonic signals in the semiconductor devices above and enhancing the performance of the semiconductor devices as a radio-frequency (RF) switch.

Abstract translation: 直接在绝缘体上半导体（SOI）衬底的掩埋绝缘体层下方形成具有与底部半导体层相同类型掺杂的第一掺杂半导体区域和具有相反类型掺杂的第二掺杂半导体区域。 第一掺杂半导体区域和第二掺杂半导体区域以不足以由于少数载流子正向偏置注入底部半导体层而引起过大电流的电压而相对于底部半导体层电接地或正向偏置，即 ，电位差不超过0.6V至0.8V。 通过顶部半导体层上的半导体器件中的电信号在感应电荷层中形成的电荷通过连接到第一和第二掺杂半导体区域的电触点排出，从而减少上述半导体器件中的谐波信号并增强性能 的半导体器件作为射频（RF）开关。

公开(公告)号：US20110131542A1

公开(公告)日：2011-06-02

申请号：US12634893

申请日：2009-12-10

Applicant: Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

Inventor： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC: G06F17/50

CPC classification number: H01L29/78603 ,  H01L21/84 ,  H01L27/1203

Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

Abstract translation: 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 任选地，在该相同部分内形成微腔，以平衡电导率的任何增加和电阻率的相应增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于这种半导体结构的方法和设计结构的实施例。

公开(公告)号：US20100244934A1

公开(公告)日：2010-09-30

申请号：US12411494

申请日：2009-03-26

Applicant: Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

Inventor： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

IPC: G11C5/14 ,  H01L29/06 ,  G06F17/50 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L21/84 ,  H01L21/76264 ,  H01L27/1203

Abstract: At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.

Abstract translation: 至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。 浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。 所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。 感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。

公开(公告)号：US20100230751A1

公开(公告)日：2010-09-16

申请号：US12538213

申请日：2009-08-10

Applicant: Alan B. Botula ,  Alvin J. Joseph ,  Alan F. Norris ,  Robert M. Rassel ,  Yun Shi

Inventor： Alan B. Botula ,  Alvin J. Joseph ,  Alan F. Norris ,  Robert M. Rassel ,  Yun Shi

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7839 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/66659

Abstract: A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of a first conductivity type, which is the opposite of the second conductivity type, on one side of a dummy gate electrode and a Schottky barrier structure surrounded by the doped guard ring on the other side. A Schottky barrier region may be laterally surrounded by the dummy gate electrode and the doped guard ring. The doped guard ring includes an unmetallized portion of a gate-side second-conductivity-type-doped semiconductor region having a doping of a second conductivity type. A Schottky barrier region may be laterally surrounded by a doped guard ring including a gate-side doped semiconductor region and a STI-side doped semiconductor region. Design structures for the inventive Schottky barrier diode are also provided.

Abstract translation: 肖特基势垒二极管包括在绝缘体上半导体（SOI）衬底中具有第二导电类型掺杂的掺杂保护环。 肖特基势垒二极管还包括在虚拟栅极电极的一侧上具有与第二导电类型相反的第一导电类型的掺杂的第一导电型掺杂半导体区域，以及被包围的肖特基势垒结构 另一侧的掺杂保护环。 肖特基势垒区域可以被伪栅电极和掺杂保护环横向包围。 掺杂保护环包括具有第二导电类型的掺杂的栅极侧第二导电型掺杂半导体区域的未金属化部分。 肖特基势垒区域可以由包括栅极掺杂半导体区域和STI侧掺杂半导体区域的掺杂保护环横向包围。 还提供了用于本发明的肖特基势垒二极管的设计结构。