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    BIPOLAR JUNCTION TRANSISTOR WITH MULTIPLE EMITTER FINGERS
    3.
    发明申请
    BIPOLAR JUNCTION TRANSISTOR WITH MULTIPLE EMITTER FINGERS 有权
    具有多个发光指示器的双极接头晶体管

    公开(公告)号：US20130119508A1

    公开(公告)日：2013-05-16

    申请号：US13294671

    申请日：2011-11-11

    申请人： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu ,  Ramana M. Malladi ,  John J. Pekarik

    发明人： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu ,  Ramana M. Malladi ,  John J. Pekarik

    IPC分类号： H01L29/73 ,  G06F17/50 ,  H01L21/331

    CPC分类号： H01L29/66303 ,  G06F17/5045 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/7322 ,  H01L29/735

    摘要： Methods for fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process.

    摘要翻译： 用于制造双极结型晶体管的方法，双极结型晶体管以及用于双极结型晶体管的设计结构。 双极结晶体管可以包括布置在不同的发射极指中的多个发射极。 形成了覆盖双极结型晶体管的非本征基极层并填充相邻发射极之间的间隙的硅化物层。 发射极侧壁上的非导电间隔物使发射体与硅化物层电绝缘。 发射极延伸通过外部基极层和硅化物层与本征基极层接触。 发射器可以在替代型工艺中使用牺牲发射器基座形成。

    Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure
    4.
    发明授权
    Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure 有权
    具有侧壁限定的内在基极到外部基极连接区域的晶体管结构和形成该结构的方法

    公开(公告)号：US08405186B2

    公开(公告)日：2013-03-26

    申请号：US12817249

    申请日：2010-06-17

    申请人： Renata Camillo-Castillo ,  Mattias E. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Russell T. Herrin ,  Alvin J. Joseph ,  Andreas D. Stricker

    发明人： Renata Camillo-Castillo ,  Mattias E. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Russell T. Herrin ,  Alvin J. Joseph ,  Andreas D. Stricker

    IPC分类号： H01L21/70

    CPC分类号： H01L29/732 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7378

    摘要： Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.

    摘要翻译： 公开了改进的晶体管结构（例如，双极晶体管（BT）结构或异质结双极晶体管（HBT）结构）的实施例以及形成晶体管结构的方法。 结构实施例可以包括夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以减少基极 电阻Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法实施例允许发射极与基极区域的自对准，并进一步允许不同特征的几何形状（例如，电介质层的厚度，导电带的宽度，电介质间隔物的宽度和介电隔离物的宽度 发射极层）进行选择性调整，以优化晶体管性能。

    Device structures for a high voltage junction field effect transistor manufactured using a hybrid orientation technology wafer and design structures for a high voltage integrated circuit
    5.
    发明授权
    Device structures for a high voltage junction field effect transistor manufactured using a hybrid orientation technology wafer and design structures for a high voltage integrated circuit 失效
    使用混合取向技术晶圆制造的高压结场效应晶体管的器件结构和用于高压集成电路的设计结构

    公开(公告)号：US07791105B2

    公开(公告)日：2010-09-07

    申请号：US12121286

    申请日：2008-05-15

    申请人： Renata Camillo-Castillo ,  Robert J. Gauthier, Jr. ,  Richard A. Phelps ,  Andreas D. Stricker

    发明人： Renata Camillo-Castillo ,  Robert J. Gauthier, Jr. ,  Richard A. Phelps ,  Andreas D. Stricker

    IPC分类号： H01L29/778

    CPC分类号： H01L29/808 ,  H01L29/0692

    摘要： Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystalline orientation, a second semiconductor layer with a second crystalline orientation, and an insulating layer between the first and second semiconductor layers. The device structure includes an epitaxial semiconductor region having the second crystalline orientation and first and second p-n junctions in the epitaxial semiconductor region. The epitaxial semiconductor region extends from the second semiconductor layer through the insulating layer and the first semiconductor layer toward a top surface of the first semiconductor layer. The first and second p-n junctions are arranged in depth within the epitaxial semiconductor region between the second semiconductor layer and the top surface of the first semiconductor layer.

    摘要翻译： 高压结场效应晶体管的器件结构和高压集成电路的设计结构。 使用具有第一晶体取向的第一半导体层，具有第二晶体取向的第二半导体层和在第一和第二半导体层之间的绝缘层的混合定向技术晶片制造器件结构。 器件结构包括具有第二晶体取向的外延半导体区域和外延半导体区域中的第一和第二p-n结。 外延半导体区域从第二半导体层延伸穿过绝缘层和第一半导体层朝向第一半导体层的顶表面延伸。 第一和第二p-n结在第二半导体层和第一半导体层的顶表面之间的外延半导体区域内被深入布置。

    Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure
    6.
    发明授权
    Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure 有权
    具有减小的集电极长度的异质结双极晶体管，制造方法和设计结构

    公开(公告)号：US09059138B2

    公开(公告)日：2015-06-16

    申请号：US13358180

    申请日：2012-01-25

    申请人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

    发明人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

    IPC分类号： H01L29/737 ,  G06F17/50 ,  H01L21/331 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10

    CPC分类号： H01L29/417 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371

    摘要： A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.

    摘要翻译： 提供异质结双极晶体管（HBT）结构，其制造方法及其设计结构。 HBT结构包括其中具有亚集电极区域的半导体衬底。 HBT结构还包括覆盖子集电极区域的一部分的集电极区域。 HBT结构还包括覆盖集电极区域的至少一部分的本征基极层。 HBT结构还包括与本征基极层相邻并电连接的外部基极层。 HBT结构还包括在外部基极层和副集电极区之间垂直延伸的隔离区。 HBT结构还包括覆盖本征基极层的一部分的发射极。 HBT结构还包括电连接到子集电极区的集电极触点。 收集器触点有利地延伸穿过外部基极层的至少一部分。