公开(公告)号：US08921190B2

公开(公告)日：2014-12-30

申请号：US12099175

申请日：2008-04-08

申请人： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

发明人： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7834 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/423 ,  H01L29/66575

摘要： A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.

摘要翻译： 提供一种半导体结构和制造方法，更具体地说，具有身体接触的场效应晶体管及其制造方法。 该结构包括具有第一导电类型的凸起源极区域和延伸到器件主体的凸起源极区域下方的有源区域的器件。 有源区具有不同于第一导电类型的第二导电类型。 接触区域与有源区域电接触。 该方法包括在器件的有源区上形成凸起的源极区域，并形成与有源区域相同的导电类型的接触区域，其中有源区域在接触区域和器件的主体之间形成接触体。

公开(公告)号：US20120168817A1

公开(公告)日：2012-07-05

申请号：US13238414

申请日：2011-09-21

申请人： Michel J. Abou-Khalil ,  Alan B. Botula ,  Alvin J. Joseph ,  Theodore J. Letavic ,  James A. Slinkman

发明人： Michel J. Abou-Khalil ,  Alan B. Botula ,  Alvin J. Joseph ,  Theodore J. Letavic ,  James A. Slinkman

IPC分类号： H01L27/088 ,  H01L21/76 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66681 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66704 ,  H01L29/66795 ,  H01L29/7436 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/785

摘要： Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage. Discrete conductive field (CF) plates are adjacent to opposing sides of the drain drift region, each having an angled sidewall such that the area between the drain drift region and the CF plate has a continuously increasing width along the length of the drain drift region from the channel region to the drain region. The CF plates can comprise polysilicon or metal structures or dopant implant regions within the same semiconductor body as the drain drift region. The areas between the CF plates and the drain drift region can comprise tapered dielectric regions or, alternatively, tapered depletion regions within the same semiconductor body as the drain drift region. Also disclosed are embodiments of a method for forming an LEDMOSFET and embodiments of a silicon-controlled rectifier (SCR) incorporating such LEDMOSFETs.

摘要翻译： 公开了具有高漏极对体击穿电压的横向延伸漏极，金属氧化物半导体，场效应晶体管（LEDMOSFET）的实施例。 离散导电场（CF）板与漏极漂移区的相对侧相邻，每侧具有成角度的侧壁，使得漏极漂移区和CF板之间的区域沿着漏极漂移区的长度具有连续增加的宽度， 沟道区到漏极区。 CF板可以包括与漏极漂移区相同的半导体主体内的多晶硅或金属结构或掺杂剂注入区。 CF板和漏极漂移区域之间的区域可以包括与漏极漂移区域相同的半导体本体内的锥形介质区域或者替代地，锥形耗尽区域。 还公开了用于形成LEDMOSFET的方法的实施例和结合了这种LEDMOSFET的可控硅整流器（SCR）的实施例。

公开(公告)号：US08021943B2

公开(公告)日：2011-09-20

申请号：US12625701

申请日：2009-11-25

申请人： Alan B. Botula ,  BethAnn Rainey ,  Daniel S. Vanslette

发明人： Alan B. Botula ,  BethAnn Rainey ,  Daniel S. Vanslette

IPC分类号： H01L21/8238

CPC分类号： H01L21/743 ,  H01L21/76224 ,  H01L21/76232

摘要： A semiconductor fabrication method comprises providing a structure which includes a semiconductor substrate having a plurality of subsurface layers, the substrate comprising a top surface and the subsurface layers comprising a top subsurface layer below the top surface of the substrate. A protective material is patterned on the top surface of the device and a material removal process is performed to simultaneously form a contact trench and an isolation trench, the material removal process removing at least a portion of the top surface and the top subsurface layer such that the contact trench and the isolation trench are formed within the subsurface layer. An insulator is then formed within the isolation trench and the contact trench is lined with the insulator. The contact trench is then filled with a conductive material such that the conductive material is deposited over the insulator.

摘要翻译： 半导体制造方法包括提供包括具有多个次表面层的半导体衬底的结构，所述衬底包括顶表面，并且所述表面下层包括在所述衬底的顶表面下方的顶部表面层。 保护材料被图案化在器件的顶表面上，并且执行材料去除工艺以同时形成接触沟槽和隔离沟槽，所述材料去除工艺去除顶表面和顶部表面下层的至少一部分，使得 接触沟槽和隔离沟槽形成在地下层内。 然后在隔离沟槽内形成绝缘体，并且接触沟槽衬有绝缘体。 然后用导电材料填充接触沟槽，使得导电材料沉积在绝缘体上。

公开(公告)号：US20110127529A1

公开(公告)日：2011-06-02

申请号：US12627343

申请日：2009-11-30

申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： H01L27/12 ,  H01L21/762

CPC分类号： H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。

公开(公告)号：US20110124177A1

公开(公告)日：2011-05-26

申请号：US12625701

申请日：2009-11-25

申请人： Alan B. Botula ,  BethAnn Rainey ,  Daniel S. Vanslette

发明人： Alan B. Botula ,  BethAnn Rainey ,  Daniel S. Vanslette

IPC分类号： H01L21/762 ,  H01L21/768

CPC分类号： H01L21/743 ,  H01L21/76224 ,  H01L21/76232

摘要： A semiconductor fabrication method comprises providing a structure which includes a semiconductor substrate having a plurality of subsurface layers, the substrate comprising a top surface and the subsurface layers comprising a top subsurface layer below the top surface of the substrate. A protective material is patterned on the top surface of the device and a material removal process is performed to simultaneously form a contact trench and an isolation trench, the material removal process removing at least a portion of the top surface and the top subsurface layer such that the contact trench and the isolation trench are formed within the subsurface layer. An insulator is then formed within the isolation trench and the contact trench is lined with the insulator. The contact trench is then filled with a conductive material such that the conductive material is deposited over the insulator.

摘要翻译： 半导体制造方法包括提供包括具有多个次表面层的半导体衬底的结构，所述衬底包括顶表面，并且所述表面下层包括在所述衬底的顶表面下方的顶部表面层。 保护材料被图案化在器件的顶表面上，并且执行材料去除工艺以同时形成接触沟槽和隔离沟槽，所述材料去除工艺去除顶表面和顶部表面下层的至少一部分，使得 接触沟槽和隔离沟槽形成在地下层内。 然后在隔离沟槽内形成绝缘体，并且接触沟槽衬有绝缘体。 然后用导电材料填充接触沟槽，使得导电材料沉积在绝缘体上。

公开(公告)号：US08916467B2

公开(公告)日：2014-12-23

申请号：US13116396

申请日：2011-05-26

申请人： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

发明人： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

IPC分类号： H03K3/01 ,  H01L21/336 ,  G06F17/50 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76251 ,  H01L21/84

摘要： A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.

摘要翻译： 具有与底部半导体层相反的导电类型的掺杂接触区域设置在底部半导体层中的掩埋绝缘体层的下方。 至少一个导电通孔结构从互连级金属线延伸穿过中间线（MOL）电介质层，顶部半导体层中的浅沟槽隔离结构，以及掩埋绝缘体层和掺杂接触区域。 掺杂接触区域被偏置在处于或接近RF开关中的峰值电压的电压，该电压去除感应电荷层内的少数电荷载流子。 少数电荷载体通过掺杂接触区域和至少一个导电通孔结构排出。 诱导电荷层中的移动电荷的快速放电减少了RF开关中的谐波产生和信号失真。 还提供了用于半导体结构的设计结构。

公开(公告)号：US08735986B2

公开(公告)日：2014-05-27

申请号：US13312442

申请日：2011-12-06

申请人： Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Robert M. Rassel ,  Mark E. Stidham

发明人： Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Robert M. Rassel ,  Mark E. Stidham

IPC分类号： H01L27/12

CPC分类号： H01L21/76224 ,  H01L21/26506 ,  H01L21/823892 ,  H01L27/04 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0802 ,  H01L27/0811 ,  H01L27/0928

摘要： A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

摘要翻译： 衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率 用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。

公开(公告)号：US08674472B2

公开(公告)日：2014-03-18

申请号：US12853532

申请日：2010-08-10

申请人： Alan B. Botula ,  Dinh Dang ,  James S. Dunn ,  Alvin J. Joseph ,  Peter J. Lindgren

发明人： Alan B. Botula ,  Dinh Dang ,  James S. Dunn ,  Alvin J. Joseph ,  Peter J. Lindgren

IPC分类号： H01L21/764

CPC分类号： H01L21/76283 ,  H01L21/76289 ,  H01L27/0738 ,  H01L27/1203 ,  H01L29/0649

摘要： A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

公开(公告)号：US08492868B2

公开(公告)日：2013-07-23

申请号：US12848558

申请日：2010-08-02

申请人： Alan B. Botula ,  Alvin J. Joseph ,  James A. Slinkman ,  Randy L. Wolf

发明人： Alan B. Botula ,  Alvin J. Joseph ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/0211 ,  H01L27/0617 ,  H01L27/1203

摘要： A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.

摘要翻译： 一种方法，集成电路和设计结构包括具有沟槽结构的硅衬底层和离子杂质植入物。 绝缘体层位于硅衬底层上并接触硅衬底层。 绝缘体层填充沟槽结构。 电路层位于掩埋绝缘体层上并与其接触。 电路层包括由被动结构分开的一组有源电路。 当从顶视图观察集成电路结构时，沟槽结构位于有源电路组之间。 因此，当从顶视图观察集成电路结构时，沟槽结构在被动结构之下并且不在电路组下方。

公开(公告)号：US20120168766A1

公开(公告)日：2012-07-05

申请号：US12983439

申请日：2011-01-03

申请人： Michel J. Abou-Khalil ,  Alan B. Botula ,  Alvin J. Joseph ,  Theodore J. Letavic ,  James A. Slinkman

发明人： Michel J. Abou-Khalil ,  Alan B. Botula ,  Alvin J. Joseph ,  Theodore J. Letavic ,  James A. Slinkman

IPC分类号： H01L29/20 ,  H01L21/76 ,  G06F17/50 ,  H01L29/78

CPC分类号： H01L29/7824 ,  G06F17/5063 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/785

摘要： A lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) with a high drain-to-body breakdown voltage (Vb) incorporates gate structure extensions on opposing sides of a drain drift region. The extensions are tapered such that a distance between each extension and the drift region increases linearly from one end adjacent to the channel region to another end adjacent to the drain region. In one embodiment, these extensions can extend vertically through the isolation region that surrounds the LEDMOSFET. In another embodiment, the extensions can sit atop the isolation region. In either case, the extensions create a strong essentially uniform horizontal electric field profile within the drain drift. Also disclosed are a method for forming the LEDMOSFET with a specific Vb by defining the dimensions of the extensions and a program storage device for designing the LEDMOSFET to have a specific Vb.

摘要翻译： 具有高漏极对体击穿电压（Vb）的横向延伸漏极，金属氧化物半导体场效应晶体管（LEDMOSFET）在漏极漂移区域的相对侧上并入门结构延伸。 延伸部是锥形的，使得每个延伸部和漂移区域之间的距离从邻近通道区域的一端线性地增加到与漏极区域相邻的另一端部。 在一个实施例中，这些扩展可以垂直延伸通过围绕LEDMOSFET的隔离区域。 在另一个实施例中，扩展可以位于隔离区域的顶部。 在任一种情况下，扩展在漏极漂移内产生强大的基本均匀的水平电场分布。 还公开了通过限定扩展的尺寸来形成具有特定Vb的LEDMOSFET的方法以及用于将LEDMOSFET设计为具有特定Vb的程序存储装置。