Abstract:
A phase locked loop (PLL) with low steady state phase errors utilizes a delay unit to delay an input signal or a reference clock so as to lower the steady state phase errors of the PLL. A calibration circuit is used to adjust the delay time of the delay unit and includes a signal generator for generating a simulation input signal and a simulation reference clock according to a phase locked clock; a delay unit for delaying the simulation reference clock and generating a delayed reference clock; a phase detector for detecting the phase error between the simulation input signal and the delayed reference clock and generating charge control signals; a charge pump and an integrator for generating an error voltage according to the charge control signals; a delay time control unit for adjusting the delay time of the delay unit according to the error voltage; and a voltage control oscillator for generating the oscillation clock according to a reference control voltage.
Abstract:
A signal calibration apparatus of a charge pump minimizes a current from the charge pump. The signal calibration apparatus includes a detecting circuit, a current adjusting circuit, and a calibrating circuit, wherein the detecting circuit is coupled to the charge pump for outputting a detecting signal according to the direction and magnitude of the current, the current adjusting circuit is coupled to the detecting circuit for outputting a calibrating signal according to the polarity and magnitude of the slew rate for the detection signal; and the calibrating circuit, which consists of a first calibration current source and a second calibration current source, is respectively coupled to the charge pump and the current adjusting circuit for adjusting the first current and the second current by outputting a first calibrating current and second calibrating current to the charge pump.
Abstract:
A submount is used for disposing an illuminant element or a light-receiving element having an optical axis. The submount is disposed at a plane and has a main body. The main body includes a first surface and a second surface. The first surface is approximately parallel to the plane and far away from the plane. The second surface is approximately parallel to the plane and adjacent to the plane. A disposing part of the first surface is tilted with respect to the second surface at a predetermined angle. The illuminant element or the light-receiving element is disposed on the disposing part. The optical axis of the illuminant element or the light-receiving element is tiled with respect to a normal of the second surface at the predetermined angle.
Abstract:
A ceramic powder composition, ceramic material, and a multi-layer ceramic capacitor fabricated thereby are provided. The ceramic powder composition includes a main ingredient and an accessory ingredient. The main ingredient is in an amount of 95 to 99 mol %, and includes BaTiO3, and the accessory ingredient is in an amount of 1 to 5 mol %, and consists of oxide Bi2O3—Tio2—XO, where X is selected from a group consisting of magnesium (Mg), vanadium (V), manganese (Mn), and chromium (Cr).
Abstract:
A complex resistance type coordinate input device includes an upper conductive structural layer, a lower conductive structural layer, and an intermediate conductive structural layer being disposed between the upper conductive structural layer and the lower conductive structural layer. The upper conductive structural layer provides an upper conductive thin layer, the lower conductive structural layer provides a lower conductive thin layer, and the intermediate conductive structural layer provides the first intermediate conductive thin layer facing the upper conductive thin layer and the second side of the intermediate conductive structural layer to form a digit-resistance type touch pad structure, and the second intermediate conductive thin layer facing the lower conductive thin layer to form an analog-resistance type touch pad structure.
Abstract:
A data retrieving and using method includes following steps: linking a designated website to obtain a corresponding webpage data, retrieving a specific key information of the corresponding webpage data by an information integrating module and/or an information integrating application software, and integrating the specific key information as an information demo zone and a hyperlink to a frame of a user interface.
Abstract:
A method for verifying a server end apparatus, suitable for verifying the identity of a server end apparatus from a client end apparatus, is provided. In the present invention, authentication data is sent to the server end apparatus by the client end apparatus, such that the server end apparatus verifies the authentication data. Afterwards, the server end apparatus must return an initial number, which is preset by the user, to the client end apparatus to verify whether the initial number is correct or not. If the initial number is incorrect, the connection with the server end apparatus is shut down. Therefore, the efficiency for verifying the server end identity is strengthened, so as to enhance the security.
Abstract:
The present invention with an optical disk drive controller and an optical pickup head connected together by a flexible cable is described. The device includes a delay adjusting module located within the first module for delaying a first signal by an amount specified by a calibration signal. The first module transmits the delayed first signal and a second signal through a first signal channel and a second signal channel, respectively, to the second module of the optical pickup head, a monitoring module located within the optical pickup head for receiving and reshaping the delayed first signal and the second signal so as to generate a monitor signal. A calibration signal-generating module is located within the optical disk drive controller for receiving the monitor signal so as to generate the calibration signal.
Abstract:
A write signal control circuit in an optical disk drive for adjusting the duty cycle of the write signals by a duty cycle adjusting unit. The write signal control circuit includes a write signal generator for converting an EFM signal into the write signals according to the write strategy waveform generating rules, a duty cycle adjusting unit for adjusting the duty cycle of each write signal according to adjusting parameters and for outputting adjusted write signals, and a duty cycle detector for detecting the duty cycle of each adjusted write signal and outputting a respective duty cycle control signal. The duty cycle adjusting unit further receives the duty cycle control signal to adapt the adjusting parameters.