公开(公告)号：US20090189656A1

公开(公告)日：2009-07-30

申请号：US12010530

申请日：2008-01-25

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/089

摘要： A delay-locked loop includes a phase detector, a shift register, a digital low pass filter, a digital to analog converter, a bias circuit, and a delay circuit. The phase detector generates a lagging signal and a leading signal corresponding to a phase difference between an input clock signal and a feedback clock signal. The shift register outputs a digital data according to the lagging signal and the leading signal. The digital low pass filter generates a selecting signal according to the digital data. The bias circuit generates a first control voltage and a second control voltage in response to the bias voltage converted from the selecting signal. The delay circuit generates the feedback clock signal corresponding to the first control voltage and the second control voltage.

摘要翻译： 延迟锁定环包括相位检测器，移位寄存器，数字低通滤波器，数模转换器，偏置电路和延迟电路。 相位检测器产生滞后信号和对应于输入时钟信号和反馈时钟信号之间的相位差的引导信号。 移位寄存器根据滞后信号和引导信号输出数字数据。 数字低通滤波器根据数字数据产生选择信号。 偏置电路响应于从选择信号转换的偏置电压产生第一控制电压和第二控制电压。 延迟电路产生对应于第一控制电压和第二控制电压的反馈时钟信号。

公开(公告)号：US20090146704A1

公开(公告)日：2009-06-11

申请号：US11951221

申请日：2007-12-05

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/093

摘要： A delay locked loop (DLL) circuit is provided. The DLL circuit includes a divider, a shift register, a digital-to-analog converter and a voltage controlled delay line. The divider divides an input clock signal to output a reference clock signal. The shift register is triggered by the reference clock signal and outputs a digital signal corresponding to the reference clock signal in accordance with a phase difference between the input clock signal and a feedback clock signal. The digital-to-analog converter transfers the digital signal output from the shift register into a control voltage. The voltage controlled delay line outputs the feedback clock signal in accordance with the control voltage transferred by the digital-to-analog converter. A method for eliminating jitter and offset between an input clock signal and an output clock signal in a delay locked loop circuit is also disclosed.

摘要翻译： 提供了延迟锁定环（DLL）电路。 DLL电路包括分频器，移位寄存器，数模转换器和电压控制延迟线。 分频器分频输入时钟信号以输出参考时钟信号。 移位寄存器由参考时钟信号触发，并根据输入时钟信号和反馈时钟信号之间的相位差输出与参考时钟信号对应的数字信号。 数模转换器将从移位寄存器输出的数字信号转换为控制电压。 电压控制延迟线根据数模转换器传输的控制电压输出反馈时钟信号。 还公开了一种在延迟锁定环电路中消除输入时钟信号和输出时钟信号之间的抖动和偏移的方法。

公开(公告)号：US09413310B2

公开(公告)日：2016-08-09

申请号：US11594774

申请日：2006-11-09

申请人： Kuo-Chan Huang ,  Chih-Haur Huang

发明人： Kuo-Chan Huang ,  Chih-Haur Huang

IPC分类号： H03F3/217

CPC分类号： H03F3/217 ,  G09G2310/0275 ,  G09G2320/0252 ,  G09G2330/021 ,  G09G2330/028 ,  H03F2200/78

摘要： A buffer circuit applied to a source driver output stage circuit includes a buffer and a D-class amplifier. The buffer is coupled to an input voltage for accordingly outputting an output voltage. The D-class amplifier includes a comparator and a switch device. The comparator is for comparing the input voltage and the output voltage and accordingly outputting a comparison signal. The switch device is coupled to an operational voltage for adjusting the output voltage according to the comparison signal.

摘要翻译： 应用于源极驱动器输出级电路的缓冲电路包括缓冲器和D级放大器。 缓冲器耦合到输入电压，从而相应地输出输出电压。 D级放大器包括比较器和开关装置。 比较器用于比较输入电压和输出电压，从而输出比较信号。 开关装置耦合到用于根据比较信号调节输出电压的工作电压。

公开(公告)号：US08352642B2

公开(公告)日：2013-01-08

申请号：US12938359

申请日：2010-11-02

申请人： Mu-Hsien Hsu ,  Chih-Haur Huang

发明人： Mu-Hsien Hsu ,  Chih-Haur Huang

IPC分类号： G06F3/00 ,  G06F1/00 ,  G06F1/04

CPC分类号： H04N21/4436 ,  G09G2330/021 ,  G09G2370/12 ,  H04N5/63 ,  H04N21/4424

摘要： The present invention provides a method and apparatus of controlling an operational status of an electronic device which receives data through a HDMI port. The present invention determines whether to wake up the electronic device from the power saving mode according to counting numbers generated based on the transitions of signals within a time period.

摘要翻译： 本发明提供一种控制通过HDMI端口接收数据的电子设备的操作状态的方法和装置。 本发明根据在一段时间内基于信号的转变产生的计数数来确定是否将电子设备从省电模式唤醒。

公开(公告)号：US20120274489A1

公开(公告)日：2012-11-01

申请号：US13096908

申请日：2011-04-28

申请人： Soon-Jyh CHANG ,  Guan-Ying Huang ,  Chun-Cheng LIU ,  CHUNG-MING HUANG ,  Jin-Fu LIN ,  Chih-Haur HUANG

发明人： Soon-Jyh CHANG ,  Guan-Ying Huang ,  Chun-Cheng LIU ,  CHUNG-MING HUANG ,  Jin-Fu LIN ,  Chih-Haur HUANG

IPC分类号： H03M1/00

CPC分类号： H03M1/462 ,  H03M1/466

摘要： A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window. The SAR controller decodes the outputs of the first and second coarse comparators and the fine comparator to obtain a converted output of the SAR ADC.

摘要翻译： 公开了逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 第一和第二电容器DAC分别接收第一和第二输入信号。 第一粗略比较器将第一电容器DAC的输出与窗口参考电压进行比较，第二粗略比较器将第二电容器DAC的输出与窗口参考电压进行比较，并且精细比较器将第一电容器DAC的输出与 第二电容DAC的输出。 SAR控制器接收第一和第二粗略比较器的输出，以确定第一和第二电容器DAC的输出是否在由窗口参考电压确定的预测窗口内。 当第一电容器DAC和第二电容器DAC的输出被确定为在预测窗口内时，SAR控制器绕过SAR ADC的至少一个模数转换阶段。 SAR控制器解码第一和第二粗略比较器和精细比较器的输出，以获得SAR ADC的转换输出。

公开(公告)号：US20120105732A1

公开(公告)日：2012-05-03

申请号：US12938359

申请日：2010-11-02

申请人： Mu-Hsien Hsu ,  Chih-Haur Huang

发明人： Mu-Hsien Hsu ,  Chih-Haur Huang

IPC分类号： H04N5/63

CPC分类号： H04N21/4436 ,  G09G2330/021 ,  G09G2370/12 ,  H04N5/63 ,  H04N21/4424

摘要： The present invention provides a method and apparatus of controlling an operational status of an electronic device which receives data through a HDMI port. The present invention determines whether to wake up the electronic device from the power saving mode according to counting numbers generated based on the transitions of signals within a time period.

摘要翻译： 本发明提供一种控制通过HDMI端口接收数据的电子设备的操作状态的方法和装置。 本发明根据在一段时间内基于信号的转变产生的计数数来确定是否将电子设备从省电模式唤醒。

公开(公告)号：US07990303B2

公开(公告)日：2011-08-02

申请号：US12639008

申请日：2009-12-16

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03M1/34 ,  H03M1/38

CPC分类号： H03M1/069 ,  H03M1/12

摘要： An analog-to-digital conversion unit (ADC unit) and an analog-to-digital converting method (ADC method) are provided. The ADC unit has a plurality of sub analog-to-digital converters and an encoding unit. Each of the employed sub analog-to-digital converters is coupled to two threshold voltages non-successive in terms of levels arrangement, compares the input voltage with the two threshold voltages and outputs two bits according to the comparison results. In this way, the difference between the two threshold voltages coupled by each of the sub analog-to-digital converters can be larger, which is advantageous in advancing the analog-to-digital converting accuracy.

摘要翻译： 提供了模数转换单元（ADC单元）和模数转换方法（ADC方法）。 ADC单元具有多个子模数转换器和编码单元。 每个采用的子模数转换器在电平排列方面被耦合到两个不连续的阈值电压，将输入电压与两个阈值电压进行比较，并根据比较结果输出两个位。 以这种方式，由每个子模数转换器耦合的两个阈值电压之间的差可以更大，这有利于提高模数转换精度。

公开(公告)号：US20110140947A1

公开(公告)日：2011-06-16

申请号：US12639008

申请日：2009-12-16

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03M1/12

CPC分类号： H03M1/069 ,  H03M1/12

摘要： An analog-to-digital conversion unit (ADC unit) and an analog-to-digital converting method (ADC method) are provided. The ADC unit has a plurality of sub analog-to-digital converters and an encoding unit. Each of the employed sub analog-to-digital converters is coupled to two threshold voltages non-successive in terms of levels arrangement, compares the input voltage with the two threshold voltages and outputs two bits according to the comparison results. In this way, the difference between the two threshold voltages coupled by each of the sub analog-to-digital converters can be larger, which is advantageous in advancing the analog-to-digital converting accuracy.

摘要翻译： 提供了模数转换单元（ADC单元）和模数转换方法（ADC方法）。 ADC单元具有多个子模数转换器和编码单元。 每个采用的子模数转换器在电平排列方面被耦合到两个不连续的阈值电压，将输入电压与两个阈值电压进行比较，并根据比较结果输出两个位。 以这种方式，由每个子模数转换器耦合的两个阈值电压之间的差可以更大，这有利于提高模数转换精度。

公开(公告)号：US20110140939A1

公开(公告)日：2011-06-16

申请号：US12639009

申请日：2009-12-16

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03M1/00

CPC分类号： G11C27/026 ,  H03M1/1295

摘要： A sample hold circuit and a method for sampling and holding a signal are provided. The sample hold circuit includes a sample unit, a direct current (DC) voltage elimination unit, and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an input signal, and the DC voltage elimination unit lowers a predetermined percentage of the DC voltage in the input signal sampled by the sample unit. When the sample hold circuit is in a second state, the DC voltage elimination unit eliminates the residual percentage of the DC voltage, and the hold unit outputs the alternating current (AC) signal in the input signal sampled by the sample unit.

摘要翻译： 提供了采样保持电路和采样和保持信号的方法。 采样保持电路包括采样单元，直流（DC）电压消除单元和保持单元。 当采样保持电路处于第一状态时，采样单元对输入信号进行采样，直流电压消除单元降低由采样单元采样的输入信号中的直流电压的预定百分比。 当采样保持电路处于第二状态时，直流电压消除单元消除直流电压的剩余百分比，并且保持单元输出由采样单元采样的输入信号中的交流（AC）信号。

公开(公告)号：US07916819B2

公开(公告)日：2011-03-29

申请号：US11907175

申请日：2007-10-10

申请人： Chih-Haur Huang

发明人： Chih-Haur Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/0996

摘要： A receiver system is provided. The receiver system includes a control unit for outputting a control signal and a selective signal, a PLL unit for generates PLL clock signals based on an initial clock signal, a phase select unit for selecting one of the PLL clock signals as a base clock signal according to the selective signal, a DLL unit for generating DLL clock signals based on the base clock signal, a sampling clock unit for generating left and right clock signals based on the DLL clock signals and a data latch unit for sampling bit data according to the left, DLL, and right clock signals to obtain left, middle and right data, which are feedback to the control unit for outputting the control signal and the selective signal to adjust the left, DLL and right clock signals or select the base clock signal for next bit data.

摘要翻译： 提供接收机系统。 接收机系统包括用于输出控制信号和选择信号的控制单元，用于基于初始时钟信号产生PLL时钟信号的PLL单元，用于选择PLL时钟信号之一作为基本时钟信号的相位选择单元， 基于所述基本时钟信号生成DLL时钟信号的DLL单元，基于所述DLL时钟信号生成左右时钟信号的采样时钟单元，以及根据左侧的位数据采样的数据锁存单元 ，DLL和右时钟信号，以获得左，中，右数据，其反馈到控制单元以输出控制信号和选择信号以调整左，右和右时钟信号或选择下一个基本时钟信号 位数据。