公开(公告)号：US08203564B2

公开(公告)日：2012-06-19

申请号：US11675662

申请日：2007-02-16

Applicant: Guofang Jiao ,  Angus M. Dorbie ,  Yun Du ,  Chun Yu ,  Jay C. Yun

Inventor： Guofang Jiao ,  Angus M. Dorbie ,  Yun Du ,  Chun Yu ,  Jay C. Yun

IPC: G06T1/20 ,  G06T1/00 ,  G06T15/40

CPC classification number: G06T15/005 ,  G06T11/40 ,  G09G5/363

Abstract: Techniques for supporting both 2-D and 3-D graphics are described. A graphics processing unit (GPU) may perform 3-D graphics processing in accordance with a 3-D graphics pipeline to render 3-D images and may also perform 2-D graphics processing in accordance with a 2-D graphics pipeline to render 2-D images. Each stage of the 2-D graphics pipeline may be mapped to at least one stage of the 3-D graphics pipeline. For example, a clipping, masking and scissoring stage in 2-D graphics may be mapped to a depth test stage in 3-D graphics. Coverage values for pixels within paths in 2-D graphics may be determined using rasterization and depth test stages in 3-D graphics. A paint generation stage and an image interpolation stage in 2-D graphics may be mapped to a fragment shader stage in 3-D graphics. A blending stage in 2-D graphics may be mapped to a blending stage in 3-D graphics.

Abstract translation: 描述了支持2-D和3-D图形的技术。 图形处理单元（GPU）可以根据3-D图形流水线执行3D图形处理以渲染3-D图像，并且还可以根据2-D图形流水线执行2-D图形处理以呈现2 -D图像。 2-D图形管线的每个阶段可以映射到3-D图形流水线的至少一个阶段。 例如，2-D图形中的裁剪，掩蔽和裁剪阶段可以映射到3D图形中的深度测试阶段。 2-D图形中路径内像素的覆盖值可以使用3-D图形中的光栅化和深度测试阶段来确定。 2-D图形中的油漆生成阶段和图像插值阶段可以映射到3-D图形中的片段着色器阶段。 2-D图形中的混合阶段可以映射到3-D图形的混合阶段。

公开(公告)号：US08193725B2

公开(公告)日：2012-06-05

申请号：US12424549

申请日：2009-04-16

Applicant: Ke-Horng Chen ,  Chun-Yu Hsieh ,  Chia-Lin Liu ,  Chi-Neng Mo ,  Hun-Wei Chen ,  Ming-Tsung Ho

Inventor： Ke-Horng Chen ,  Chun-Yu Hsieh ,  Chia-Lin Liu ,  Chi-Neng Mo ,  Hun-Wei Chen ,  Ming-Tsung Ho

IPC: G05F1/00

CPC classification number: H05B33/0827 ,  H02M3/156 ,  H05B33/0815 ,  Y02B20/347

Abstract: A backlight module control system includes a plurality of backlight sub-modules, a control signals output unit, a voltage converter and a plurality of current control units. The control signals output circuit is for providing a voltage control signal, a current control signal and a plurality of PWM signals; the voltage converter is coupled to the control signals output circuit and the backlight sub-modules, and is for outputting an output voltage to the backlight sub-modules according to the voltage control signal; the current control units are coupled to the backlight sub-modules, respectively, and each current control unit is for determining a current of its corresponding backlight sub-module according to the current control signal, and each current control unit is further utilized for determining whether its corresponding backlight sub-module is enabled or not according to its corresponding PWM signal. In addition, only one backlight module is enabled at a same time.

Abstract translation: 背光模块控制系统包括多个背光子模块，控制信号输出单元，电压转换器和多个电流控制单元。 控制信号输出电路用于提供电压控制信号，电流控制信号和多个PWM信号; 电压转换器耦合到控制信号输出电路和背光子模块，并用于根据电压控制信号将输出电压输出到背光子模块; 电流控制单元分别耦合到背光子模块，并且每个电流控制单元用于根据当前控制信号确定其对应的背光子模块的电流，并且每个电流控制单元进一步用于确定是否 其对应的背光子模块根据其相应的PWM信号使能或不使能。 此外，只有一个背光模块同时启用。

公开(公告)号：US20120081980A1

公开(公告)日：2012-04-05

申请号：US12897078

申请日：2010-10-04

Applicant: Chun-Yu Chiu

Inventor： Chun-Yu Chiu

IPC: G11C7/00

CPC classification number: G11C11/413 ,  G11C7/227

Abstract: A memory including a memory cell array, a word line decoder, a first and a second reference bit line generators are provided. The memory cell array has first and last bit lines respectively disposed at two sides of the memory cell array. The word line decoder generates a pre-word line signal. The first and the second reference bit line generators respectively detect voltage level variations of the first and last bit lines according to the pre-word line signal, so as to generate a first and a second cut-back signals. The first reference bit line generator transmits the first cut-back signal to the second reference bit line generator, the second reference bit line generator transmits the first and the second cut-back signals to the word line decoder, and the word line decoder generates a word line signal according to the first and the second cut-back signals and the pre-word line signal.

Abstract translation: 提供了包括存储单元阵列，字线解码器，第一和第二参考位线发生器的存储器。 存储单元阵列具有分别设置在存储单元阵列的两侧的第一和最后位线。 字线解码器产生预字线信号。 第一和第二参考位线发生器分别根据预字线信号检测第一和最后位线的电压电平变化，以产生第一和第二切断信号。 第一参考位线发生器将第一切断信号发送到第二参考位线发生器，第二参考位线发生器将第一和第二切断信号发送到字线解码器，并且字线解码器产生 根据第一和第二切断信号和预字线信号的字线信号。

公开(公告)号：US08089834B2

公开(公告)日：2012-01-03

申请号：US13009668

申请日：2011-01-19

Applicant: Chia-Wei Liao ,  Chih-Ching Chen ,  Yuh Chen ,  Ming-Jiou Yu ,  Kuo-Jung Lan ,  Chun-Yu Lin ,  Shu-Hung Chou

Inventor： Chia-Wei Liao ,  Chih-Ching Chen ,  Yuh Chen ,  Ming-Jiou Yu ,  Kuo-Jung Lan ,  Chun-Yu Lin ,  Shu-Hung Chou

IPC: G11B7/00

CPC classification number: G11B7/0941 ,  G11B7/0903

Abstract: The invention provides an apparatus for controlling servo signal gains of an optical disc drive. The apparatus adjusts the gains of a plurality of servo signals controlling a servo system of the optical disc drive when the optical disk drive encounters an operating state transition. In a first mode, at least one AGC loop of the apparatus compensates the gains of the servo signals with a selectable bandwidth during a specific period after the operating state transition to accelerate the convergence of the servo signals. In a second mode, at least one AGC loop of the apparatus reloads the previously saved convergence values or pre-determined values as the initial values according to the current operating state immediately after the operating state transition to accelerate the convergence of the servo signals.

Abstract translation: 本发明提供一种用于控制光盘驱动器的伺服信号增益的装置。 当光盘驱动器遇到操作状态转换时，该装置调节控制光盘驱动器的伺服系统的多个伺服信号的增益。 在第一模式中，该装置的至少一个AGC环路在操作状态转换之后的特定时段期间以可选择的带宽补偿伺服信号的增益，以加速伺服信号的收敛。 在第二模式中，装置的至少一个AGC环路根据紧接在运行状态转换之后的当前运行状态重新加载先前存储的收敛值或预定值作为初始值，以加速伺服信号的收敛。

公开(公告)号：US20110286059A1

公开(公告)日：2011-11-24

申请号：US12783709

申请日：2010-05-20

Applicant: Xian-Jun Wang ,  Ming-Jie Zhao ,  Jian-Chun Yu

Inventor： Xian-Jun Wang ,  Ming-Jie Zhao ,  Jian-Chun Yu

IPC: H04N1/04

CPC classification number: H04N1/047 ,  H04N1/00352 ,  H04N1/00363 ,  H04N1/00368 ,  H04N1/00968 ,  H04N1/121 ,  H04N1/193 ,  H04N2201/0418 ,  H04N2201/0422 ,  H04N2201/0471 ,  H04N2201/04732 ,  H04N2201/04737 ,  H04N2201/04756 ,  H04N2201/04767

Abstract: An image scanning device and an image scanning method are provided. The invention is related to a miniaturized image scanning device and an image scanning method. The miniaturized image scanning device includes a housing, a first driving roller set, an entrance sensor, an image sensor, a reflective light source, a transmissive light source, and a control module. The housing has an entrance and an exit. The first driving roller set is disposed in the housing. The entrance sensor is disposed between the entrance and the first driving roller set. The image sensor, the reflective light source and the transmissive light source are disposed between the first driving roller set and the exit. The control module receives and processes signals outputted from the image sensor and the entrance sensor to control the operation of the image sensor, the first driving roller set, the reflective light source and the transmissive light source.

Abstract translation: 提供了图像扫描装置和图像扫描方法。 本发明涉及一种小型化图像扫描装置和图像扫描方法。 小型化图像扫描装置包括壳体，第一驱动辊组，入射传感器，图像传感器，反射光源，透射光源和控制模块。 房屋有入口和出口。 第一驱动辊组设置在壳体中。 入口传感器设置在入口和第一驱动辊组之间。 图像传感器，反射光源和透射光源设置在第一驱动辊组和出口之间。 控制模块接收并处理从图像传感器和入口传感器输出的信号，以控制图像传感器，第一驱动辊组，反射光源和透射光源的操作。

公开(公告)号：US08013709B2

公开(公告)日：2011-09-06

申请号：US12714441

申请日：2010-02-27

Applicant: Sheng-Nan Tsai ,  Yi-Fan Wu ,  Yung-Sheng Yeh ,  Jia-Li Tsai ,  Chia-Cheng Yang ,  Yung-Yu Chang ,  Tsung-Sheng Yeh ,  Hua-Sheng Lin ,  Chun-Yu Hou ,  Tsung-Hsiao Wu

Inventor： Sheng-Nan Tsai ,  Yi-Fan Wu ,  Yung-Sheng Yeh ,  Jia-Li Tsai ,  Chia-Cheng Yang ,  Yung-Yu Chang ,  Tsung-Sheng Yeh ,  Hua-Sheng Lin ,  Chun-Yu Hou ,  Tsung-Hsiao Wu

IPC: H01F27/30 ,  H01F27/06 ,  H01F21/06 ,  H01F21/04 ,  H01F27/28

CPC classification number: H01F27/2847 ,  H01F27/30

Abstract: The present invention provides a conductive module used for assembling a magnetic element and an electronic component. The conductive module includes a conductive base, an electronic component and a plurality of conductive units. The electronic component is electrically connected to the conductive base and disposed on one side of the conductive base. The conductive units have respective hollow portions. The conductive units are spaced from each other and fixed on the conductive base such that the hollow portions of the conductive units are aligned with each other to define a channel.

Abstract translation: 本发明提供一种用于组装磁性元件和电子元件的导电模块。 导电模块包括导电基座，电子部件和多个导电单元。 电子部件电连接到导电基底并且设置在导电基底的一侧。 导电单元具有相应的中空部分。 导电单元彼此间隔开并固定在导电基底上，使得导电单元的中空部分彼此对准以限定通道。

公开(公告)号：US08013648B1

公开(公告)日：2011-09-06

申请号：US12835166

申请日：2010-07-13

Applicant: Lieh-Chiu Lin ,  Chun-Yu Chiu

Inventor： Lieh-Chiu Lin ,  Chun-Yu Chiu

IPC: H03K5/12

CPC classification number: H03K5/04 ,  H03K19/00361 ,  H04L25/026

Abstract: An output slew-rate controlled interface is provided. The output slew-rate controlled interface includes: a standard slew-rate range generating circuit, for generating at least one standard signal defining a standard slew-rate range; a slew-rate comparing circuit, coupled to the standard slew-rate range generating circuit and a load circuit coupled to the interface, for comparing a response slew-rate of a response signal from the load circuit with the standard slew-rate range and producing a comparison result; and an outputting circuit, coupled to the slew-rate comparing circuit, for adjusting an output slew-rate of an output signal according to the comparison result and outputting the output signal to the load circuit.

Abstract translation: 提供输出转换速率控制接口。 输出转换速率控制接口包括：标准转换速率范围发生电路，用于产生定义标准转换速率范围的至少一个标准信号; 耦合到标准压摆率范围产生电路的转换速率比较电路和耦合到该接口的负载电路，用于将来自负载电路的响应信号的响应转换速率与标准转换速率范围进行比较，并产生 比较结果; 以及输出电路，其耦合到所述转换速率比较电路，用于根据所述比较结果调整输出信号的输出转换速率，并将所述输出信号输出到所述负载电路。

公开(公告)号：US08009172B2

公开(公告)日：2011-08-30

申请号：US11550344

申请日：2006-10-17

Applicant: Guofang Jiao ,  Brian Ruttenberg ,  Chun Yu ,  Yun Du

Inventor： Guofang Jiao ,  Brian Ruttenberg ,  Chun Yu ,  Yun Du

IPC: G06T1/20

CPC classification number: G06T15/005

Abstract: This disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Unlike conventional GPU pipelines, for example, an attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU by the attribute gradient setup and attribute interpolator stages. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies.

Abstract translation: 本公开描述了使用一个或多个共享算术逻辑单元（ALU）的图形处理单元（GPU）流水线。 为了促进ALU的这种共享，所公开的GPU流水线的阶段可以相对于传统的GPU管线重新排列。 此外，通过重新排列GPU流水线的各个阶段，可以在图像处理中实现效率。 与传统GPU流水线不同，例如，属性梯度建立阶段可以在流水线后面定位，属性内插器阶段可以立即跟随属性梯度建立阶段。 这允许通过属性渐变设置和属性内插器阶段共享ALU。 还描述了用于GPU流水线的若干其它技术和特征，这可以提高性能并可能实现额外的处理效率。

公开(公告)号：US20110207409A1

公开(公告)日：2011-08-25

申请号：US12711302

申请日：2010-02-24

Applicant: Ming-Do KER ,  Chun-Yu LIN

Inventor： Ming-Do KER ,  Chun-Yu LIN

IPC: H04B1/00 ,  H01L27/06 ,  H01L23/60

CPC classification number: H01L27/0262

Abstract: A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier comprising an alternating arrangement of a first P-type semiconductor material, a first N-type semiconductor material, a second P-type semiconductor material and a second N-type semiconductor material electrically coupled between an anode and a cathode. The anode is electrically coupled to the first P-type semiconductor material and the cathode is electrically coupled to the second N-type semiconductor material. The ESD protection circuit further includes an inductor electrically coupled between the anode and the second P-type semiconductor material or between the cathode and the first N-type semiconductor material.

Abstract translation: 代表性静电放电（ESD）保护电路包括可控硅整流器，其包括第一P型半导体材料，第一N型半导体材料，第二P型半导体材料和第二N型半导体材料的交替布置 电耦合在阳极和阴极之间的材料。 阳极电耦合到第一P型半导体材料，并且阴极电耦合到第二N型半导体材料。 ESD保护电路还包括电耦合在阳极和第二P型半导体材料之间或在阴极和第一N型半导体材料之间的电感器。

公开(公告)号：US08004569B2

公开(公告)日：2011-08-23

申请号：US12010529

申请日：2008-01-25

Applicant: Chih-Shih Yu ,  Chun-Yu Chen ,  Chih-Ying Tu

Inventor： Chih-Shih Yu ,  Chun-Yu Chen ,  Chih-Ying Tu

IPC: H04N5/228

CPC classification number: H04N5/23248 ,  H04N5/23277

Abstract: A method for obtaining a still image frame with anti-vibration clearness includes the following steps. Multiple raw image frames are captured during a capturing period according to a capturing instruction. The raw image frames are compressed respectively, according to a predetermined compression rule, into multiple compressed image frames each of which has a data length after such compression. The compressed image frames are stored according to a predetermined sequence. The data lengths of the compressed image frames stored are compared according to the predetermined sequence. The desired still image frame is obtained through the compressed image frame of which the data length has a unique feature among all the compressed image frames.

Abstract translation: 用于获得具有抗振动清晰度的静止图像帧的方法包括以下步骤。 根据捕获指令在拍摄期间捕获多个原始图像帧。 原始图像帧根据预定的压缩规则被分别压缩成多个压缩图像帧，每个压缩图像帧在这样的压缩之后具有数据长度。 按照预定顺序存储压缩图像帧。 存储的压缩图像帧的数据长度根据预定顺序进行比较。 通过压缩图像帧获得所需的静止图像帧，其中数据长度在所有压缩图像帧中具有独特的特征。