公开(公告)号：US20140351609A1

公开(公告)日：2014-11-27

申请号：US14286432

申请日：2014-05-23

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE ,  Etron Technology, Inc.

Inventor： Chun SHIAH ,  Bor-Doou RONG

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3296 ,  Y02D10/14 ,  Y02D10/172

Abstract: A memory with variable operation voltage is disclosed. The disclosed DRAM comprises a core memory module, a register, and a first voltage adjustment module. The core memory module operates with a first control voltage. The register is used for storing a plurality of control signals and selecting one among the control signals as a voltage control signal according to an input signal. The first voltage adjustment module is respectively electrically connected to the register, the core memory module, and an external voltage, so as to provide the first control voltage according to the voltage control signal and the external voltage.

Abstract translation: 公开了具有可变工作电压的存储器。 所公开的DRAM包括核心存储器模块，寄存器和第一电压调节模块。 核心存储器模块以第一控制电压工作。 寄存器用于存储多个控制信号，并且根据输入信号将控制信号中的一个选择为电压控制信号。 第一电压调节模块分别电连接到寄存器，核心存储器模块和外部电压，以便根据电压控制信号和外部电压提供第一控制电压。

公开(公告)号：US20140043888A1

公开(公告)日：2014-02-13

申请号：US13772342

申请日：2013-02-21

Applicant: ETRON TECHNOLOGY, INC.

Inventor： Ho-Yin Chen ,  Shi-Huei Liu

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C11/40615 ,  G11C11/4063

Abstract: The latency of a PSRAM is set according to its current state when receiving an external command. If the PSRAM is not executing a specific operation or has completed the specific operation while meeting corresponding timing parameters, the PSRAM is configured to execute the external command with a first latency. If the PSRAM is executing the specific operation or has completed the specific operation before meeting corresponding timing parameters, the PSRAM is configured to execute the external command with a second latency larger than the first latency.

Abstract translation: 当接收到外部命令时，根据其当前状态设置PSRAM的延迟。 如果PSRAM没有执行特定操作或者在满足相应的定时参数的情况下完成了特定操作，则PSRAM被配置为以第一等待时间执行外部命令。 如果PSRAM正在执行特定操作或者在满足相应的定时参数之前完成了特定操作，则PSRAM被配置为以大于第一等待时间的第二等待时间来执行外部命令。

公开(公告)号：US20130346679A1

公开(公告)日：2013-12-26

申请号：US13873260

申请日：2013-04-30

Applicant: ETRON TECHNOLOGY, INC.

Inventor： Wen-Min Lu

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/00 ,  G06F7/58 ,  G06F7/582 ,  G06F7/584 ,  G06F12/0246 ,  G06F21/60

Abstract: A system of generating scramble data includes a linear feedback shift register and a scramble engine. The linear feedback shift register is used for generating a plurality of first scramble values according to an initial value. The scramble engine is coupled to the linear feedback shift register for utilizing at least one bit of a first scramble value of the plurality of first scramble values to execute a first logic operation on other bits of the first scramble value to generate a second scramble value corresponding to the first scramble value. A bit number of the second scramble value is the same as a bit number of the first scramble value.

Abstract translation: 产生加扰数据的系统包括线性反馈移位寄存器和加扰引擎。 线性反馈移位寄存器用于根据初始值产生多个第一扰频值。 加扰引擎耦合到线性反馈移位寄存器，用于利用多个第一加扰值的第一加扰值的至少一个比特来对第一加扰值的其他比特执行第一逻辑运算以产生对应的第二加扰值 到第一个争夺的价值。 第二加扰值的位数与第一加扰值的位数相同。

公开(公告)号：US20130250711A1

公开(公告)日：2013-09-26

申请号：US13743350

申请日：2013-01-17

Applicant: ETRON TECHNOLOGY, INC.

Inventor： Chun Shiah ,  Sen-Fu Hong

IPC: G11C11/402

CPC classification number: G11C11/402 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618

Abstract: A memory includes a determination circuit, a plurality of refresh counters, and a plurality of banks. The determination circuit receives a refresh command. The plurality of refresh counters are coupled to the determination circuit. Each refresh counter of the plurality of refresh counters corresponds to one bank of the plurality of banks. The determination circuit detects whether a first bank of the plurality of banks is enabled or a number counted by a first refresh counter of the plurality of refresh counters corresponding to the first bank is equal to a predetermined value. Then, the determination circuit optionally refreshes one bank of the plurality of banks according to a detection result. Thus, the memory still refreshes an idle bank according to a refresh command even if the plurality of banks are not all idle.

Abstract translation: 存储器包括确定电路，多个刷新计数器和多个存储体。 确定电路接收刷新命令。 多个刷新计数器耦合到确定电路。 多个刷新计数器的每个刷新计数器对应于多个存储体中的一个存储体。 确定电路检测多个组的第一组是否被使能，或者由对应于第一组的多个刷新计数器的第一刷新计数器计数的数量等于预定值。 然后，确定电路根据检测结果可选地刷新多个存储体中的一个存储体。 因此，即使多个存储体都不是空闲，存储器仍然根据刷新命令刷新空闲存储体。

公开(公告)号：US20130234694A1

公开(公告)日：2013-09-12

申请号：US13787837

申请日：2013-03-07

Applicant: ETRON TECHNOLOGY, INC.

Inventor： Yen-An Chang ,  Yi-Hao Chang

IPC: G05F3/02

CPC classification number: G06F3/02 ,  G05F1/575 ,  G05F3/02

Abstract: An initial voltage generation circuit includes a reference voltage generator, a reference voltage selector, at least one initial voltage level regulator, and a plurality of stabilization capacitors. The reference voltage generator generates a plurality of reference voltage candidate groups. The reference voltage selector includes a plurality of selection switch groups and a plurality of switch control circuits. Each selection switch group includes a plurality of parallel switches. Each switch control circuit corresponds to a selection switch group for generating a switch signal to control the selection switch group to output a reference voltage candidate of a corresponding reference voltage candidate group. Each initial voltage level regulator generates an inner reference voltage according to a power-up signal, and a stabilization capacitor corresponding to the initial voltage level regulator is used for stabilizing the inner reference voltage.

Abstract translation: 初始电压产生电路包括参考电压发生器，参考电压选择器，至少一个初始电压电平调节器和多个稳定电容器。 参考电压发生器产生多个参考电压候选组。 参考电压选择器包括多个选择开关组和多个开关控制电路。 每个选择开关组包括多个并联开关。 每个开关控制电路对应于选择开关组，用于产生开关信号以控制选择开关组以输出相应参考电压候选组的参考电压候选。 每个初始电压电平调节器根据上电信号产生内部参考电压，并且使用与初始电压电平调节器相对应的稳定电容器来稳定内部参考电压。

公开(公告)号：US20130234684A1

公开(公告)日：2013-09-12

申请号：US13787823

申请日：2013-03-07

Applicant: ETRON TECHNOLOGY, INC.

Inventor： Yen-An Chang ,  Kuang-Fu Teng ,  Der-Min Yuan

IPC: G05F1/46

CPC classification number: G05F1/468 ,  G05F1/575

Abstract: An immediate response low dropout regulation system includes a low dropout regulation unit, a tracking voltage generation unit, and a self-driving unit. The low dropout regulation unit is used for generating and outputting an inner output voltage according to a reference voltage. The tracking voltage generation unit is used for generating and outputting a tracking voltage according to the reference voltage. The self-driving unit is coupled to the low dropout regulation unit and the tracking voltage generation unit. When a voltage difference between the tracking voltage and the inner output voltage is greater than a constant times threshold voltage, the self-driving unit provides a compensation current to an output terminal of the low dropout regulation unit.

Abstract translation: 立即响应的低压差调节系统包括低压差调节单元，跟踪电压产生单元和自驱动单元。 低压差调节单元用于根据参考电压产生和输出内部输出电压。 跟踪电压产生单元用于根据参考电压产生和输出跟踪电压。 自驱动单元耦合到低压差调节单元和跟踪电压产生单元。 当跟踪电压和内部输出电压之间的电压差大于恒定时间阈值电压时，自驱动单元向低压差调节单元的输出端提供补偿电流。

公开(公告)号：US20250139033A1

公开(公告)日：2025-05-01

申请号：US19008669

申请日：2025-01-03

Applicant: Etron Technology, Inc.

Inventor： Chun Shiah

IPC: G06F13/20

Abstract: A memory chip includes a plurality of memory banks, an I/O data bus, and a plurality of align circuits. Each memory bank outputs or receives a data set in parallel. The plurality of align circuits correspond to the plurality of memory banks respectively. The data set of one memory bank is transferred to one corresponding align circuit which then simultaneously transfers the data set to the I/O data bus in parallel, or the data set is transferred from the I/O data bus to the one corresponding align circuit which then simultaneously transfers the data set to the one memory bank in parallel. There is no parallel-to-serial circuit and serial-to-parallel circuit between the I/O data bus and each memory banks.

公开(公告)号：US20250046362A1

公开(公告)日：2025-02-06

申请号：US18793955

申请日：2024-08-05

Applicant: Etron Technology, Inc.

Inventor： Chun Shiah

IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/4097

Abstract: A hybrid memory chip as well as a memory system and a computing apparatus including the hybrid memory chip are provided. The hybrid memory chip includes: dynamic random access memory (DRAM) arrays; sense amplifier arrays, disposed around each of the DRAM arrays; and static random access memory (SRAM) arrays, disposed around each of the DRAM arrays, and respectively abutted with one of the sense amplifier arrays. The sense amplifier arrays are configured to perform read operations from the DRAM arrays and the SRAM arrays. Bit lines across the DRAM arrays extend through the sense amplifier arrays and the SRAM arrays.

公开(公告)号：US20250038067A1

公开(公告)日：2025-01-30

申请号：US18785296

申请日：2024-07-26

Applicant: nD-HI Technologies Lab, Inc. ,  ETRON TECHNOLOGY, INC.

Inventor： Ho-Ming Tong ,  Chih-Hsun HSIEH ,  Chao-Chun LU

IPC: H01L23/373 ,  H01L23/467 ,  H01L23/528 ,  H10B10/00

Abstract: A semiconductor device includes a substrate, a memory component and a heat dissipation component. The memory component is disposed on the substrate. The heat dissipation component is disposed on the substrate. The heat dissipation component has a thermal conductivity greater than that of silicon.

公开(公告)号：US12183822B2

公开(公告)日：2024-12-31

申请号：US17314233

申请日：2021-05-07

Applicant: Invention And Collaboration Laboratory Pte. Ltd. ,  ETRON TECHNOLOGY, INC.

Inventor： Chao-Chun Lu

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: The present invention provides a new MOSFET structure with controllable channel length by forming lightly doped drains without using ion implantation. The MOSFET structure comprises a semiconductor wafer substrate with a semiconductor surface, a gate structure over the semiconductor surface, a channel region under the semiconductor surface, and a first conductive region electrically coupled to the channel region. The first conductive region comprises a lightly doped drain region independent from the semiconductor wafer substrate.