-
1.发明申请公开(公告)号：US20180068693A1
公开(公告)日：2018-03-08
申请号：US15696200
申请日：2017-09-06
Applicant: Etron Technology, Inc.
Inventor： Chun Shiah , Ho-Yin Chen , Cheng-Nan Chang
IPC: G11C7/08
CPC classification number: G11C7/08 , G11C11/40615 , G11C11/408 , G11C11/4096 , G11C29/46 , G11C29/50016 , G11C2029/5602
Abstract: A circuit for outputting information of a memory circuit during a self-refresh mode includes a driver. The driver is coupled to a self-refresh control circuit and a self-refresh address counter. The driver is used for driving a plurality of pads of the memory circuit to output information of a plurality of inner signals corresponding to a self-refresh mode signal, and output information of addresses of a plurality of word lines of the memory circuit when the self-refresh mode signal and a test mode signal are enabled and the memory circuit enters the self-refresh mode. Each word line of the plurality of word lines corresponds to an inner signal of the plurality of inner signals.
-
公开(公告)号：US20140050038A1
公开(公告)日：2014-02-20
申请号：US13849557
申请日：2013-03-25
Applicant: ETRON TECHNOLOGY, INC.
Inventor： Ho-Yin Chen , Hung-Jen Chang , Chun Shiah
IPC: G11C29/02
CPC classification number: G11C29/023 , G11C7/227 , G11C8/08 , G11C11/4076 , G11C29/50012 , G11C2029/1202
Abstract: A memory device includes a DRAM, a first bi-directional tracking circuit and a second bi-directional tracking circuit. The DRAM includes a cell, a word line and a bit line. The first bi-directional tracking circuit is configured to track a first timing constraint associated with turning on or turning off the word line. The second bi-directional tracking circuit is configured to track a second timing constraint associated with turning on the bit line, turning off the bit line, or accessing the cell via the bit line.
Abstract translation: 存储器件包括DRAM，第一双向跟踪电路和第二双向跟踪电路。 DRAM包括单元，字线和位线。 第一双向跟踪电路被配置为跟踪与打开或关闭字线相关联的第一定时约束。 第二双向跟踪电路被配置为跟踪与打开位线相关联的第二定时约束，关闭位线或经由位线访问单元。
-
3.发明公开公开(公告)号：US20240330107A1
公开(公告)日：2024-10-03
申请号：US18623024
申请日：2024-03-31
Applicant: Etron Technology, Inc.
Inventor： Ho-Yin Chen , Ting-Feng Chang , Bo-Han Zhang
IPC: G06F11/10
CPC classification number: G06F11/1004
Abstract: A memory includes a plurality of e-fuse sets, a sensing circuit, an Error-Correcting Code (ECC) circuit, and a plurality of registers. Each e-fuse set includes a plurality of e-fuses, and each e-fuse of the plurality of e-fuses corresponds to a first blown result. The sensing circuit senses the plurality of e-fuses to output a plurality of first blown results. The ECC circuit receives the plurality of first blown results and corrects a first blown result if the first blown result includes an error or directly outputs the first blown result if the first blown result comprises no error to generate a second blown result. The plurality of registers receive a plurality of second blown results. The plurality of second blown results adjusts predetermined settings of the memory, and a number of the plurality of registers is less than a number of the plurality of e-fuses.
-
公开(公告)号：US08917568B2
公开(公告)日：2014-12-23
申请号：US13772342
申请日：2013-02-21
Applicant: Etron Technology, Inc.
Inventor： Ho-Yin Chen , Shi-Huei Liu
IPC: G11C7/00 , G11C11/419 , G11C11/4063 , G11C11/406
CPC classification number: G11C11/419 , G11C11/40615 , G11C11/4063
Abstract: The latency of a PSRAM is set according to its current state when receiving an external command. If the PSRAM is not executing a specific operation or has completed the specific operation while meeting corresponding timing parameters, the PSRAM is configured to execute the external command with a first latency. If the PSRAM is executing the specific operation or has completed the specific operation before meeting corresponding timing parameters, the PSRAM is configured to execute the external command with a second latency larger than the first latency.
Abstract translation: 当接收到外部命令时，根据其当前状态设置PSRAM的延迟。 如果PSRAM没有执行特定操作或者在满足相应的定时参数的情况下完成了特定操作，则PSRAM被配置为以第一等待时间执行外部命令。 如果PSRAM正在执行特定操作或者在满足相应的定时参数之前完成了特定操作，则PSRAM被配置为以大于第一等待时间的第二等待时间来执行外部命令。
-
5.发明授权公开(公告)号：US12224768B2
公开(公告)日：2025-02-11
申请号：US18217892
申请日：2023-07-03
Applicant: ETRON TECHNOLOGY, INC.
Inventor： Ho-Yin Chen , Han-Hsien Wang , Han-Nung Yeh
Abstract: An error correction method comprises: when a decoder determines that an input analog code is at a forbidden state, setting a digital binary code as a first predetermined code and inputting the digital binary code to an ECC engine; determining whether the digital binary code has no error or two errors; when the digital binary code has no error, outputting the digital binary code after ECC by the ECC engine; when the digital binary code has two errors, resetting the digital binary code as a second predetermined code and inputting the digital binary code to the ECC engine for ECC; and when the decoder determines that the input analog code is not at the forbidden state, decoding the input analog code into the digital binary code and inputting the digital binary code to the ECC engine for ECC.
-
Patent Agency Ranking
6.发明授权公开(公告)号：US11736121B1
公开(公告)日：2023-08-22
申请号：US17827029
申请日：2022-05-27
Applicant: ETRON TECHNOLOGY, INC.
Inventor： Ho-Yin Chen , Han-Hsien Wang , Han-Nung Yeh
CPC classification number: H03M13/098 , H03M13/1108 , H03M13/6597
Abstract: An error correction method comprises: when a decoder determines that an input analog code is at a forbidden state, setting a digital binary code as a first predetermined code and inputting the digital binary code to an ECC engine; determining whether the digital binary code has no error or two errors; when the digital binary code has no error, outputting the digital binary code after ECC by the ECC engine; when the digital binary code has two errors, resetting the digital binary code as a second predetermined code and inputting the digital binary code to the ECC engine for ECC; and when the decoder determines that the input analog code is not at the forbidden state, decoding the input analog code into the digital binary code and inputting the digital binary code to the ECC engine for ECC.
-
公开(公告)号：US10037787B2
公开(公告)日：2018-07-31
申请号：US15696200
申请日：2017-09-06
Applicant: Etron Technology, Inc.
Inventor： Chun Shiah , Ho-Yin Chen , Cheng-Nan Chang
CPC classification number: G11C7/08 , G11C11/40615 , G11C11/408 , G11C11/4096 , G11C29/46 , G11C29/50016 , G11C2029/5602
Abstract: A circuit for outputting information of a memory circuit during a self-refresh mode includes a driver. The driver is coupled to a self-refresh control circuit and a self-refresh address counter. The driver is used for driving a plurality of pads of the memory circuit to output information of a plurality of inner signals corresponding to a self-refresh mode signal, and output information of addresses of a plurality of word lines of the memory circuit when the self-refresh mode signal and a test mode signal are enabled and the memory circuit enters the self-refresh mode. Each word line of the plurality of word lines corresponds to an inner signal of the plurality of inner signals.
-
公开(公告)号：US20140043888A1
公开(公告)日：2014-02-13
申请号：US13772342
申请日：2013-02-21
Applicant: ETRON TECHNOLOGY, INC.
Inventor： Ho-Yin Chen , Shi-Huei Liu
IPC: G11C11/419
CPC classification number: G11C11/419 , G11C11/40615 , G11C11/4063
Abstract: The latency of a PSRAM is set according to its current state when receiving an external command. If the PSRAM is not executing a specific operation or has completed the specific operation while meeting corresponding timing parameters, the PSRAM is configured to execute the external command with a first latency. If the PSRAM is executing the specific operation or has completed the specific operation before meeting corresponding timing parameters, the PSRAM is configured to execute the external command with a second latency larger than the first latency.
Abstract translation: 当接收到外部命令时，根据其当前状态设置PSRAM的延迟。 如果PSRAM没有执行特定操作或者在满足相应的定时参数的情况下完成了特定操作，则PSRAM被配置为以第一等待时间执行外部命令。 如果PSRAM正在执行特定操作或者在满足相应的定时参数之前完成了特定操作，则PSRAM被配置为以大于第一等待时间的第二等待时间来执行外部命令。
-
公开(公告)号：US20240331797A1
公开(公告)日：2024-10-03
申请号：US18623070
申请日：2024-04-01
Applicant: Etron Technology, Inc.
Inventor： Ho-Yin Chen , Po-Hung Yang , Chun-Chia Chen
IPC: G11C29/56
CPC classification number: G11C29/56016 , G11C29/56008 , G11C2029/5602
Abstract: A memory with e-fuses includes a receiving circuit and a plurality of e-fuse groups. Each e-fuse group of the e-fuse groups is coupled to the receiving circuit through a corresponding bus group. The receiving circuit receives a plurality of blown signal sets each time and transmits each of the blown signal sets to a e-fuse group, and predetermined e-fuses of the e-fuse group are blown according to the each of the blown signal sets to adjust predetermined settings of the memory, and the each of the blown signal sets only corresponds to the e-fuse group. A number of the plurality of blown signal sets is not greater than a number of the e-fuse groups.
-
公开(公告)号：US11494260B2
公开(公告)日：2022-11-08
申请号：US16223136
申请日：2018-12-18
Applicant: Etron Technology, Inc.
Inventor： Ho-Yin Chen , Ting-Feng Chang , Chun-Chia Chen
Abstract: A memory with an error correction function includes a controller and a memory cell array. The controller optionally writes written data to a normal storage area and a backup area of the memory cell array, and when the controller reads first data corresponding to the written data from the normal storage area, if at least two errors are included in the first data, the controller reads the backup area to output second data corresponding to the written data from the backup area.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.012 seconds)
