公开(公告)号：US11729030B2

公开(公告)日：2023-08-15

申请号：US17692230

申请日：2022-03-11

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Yi-Che Tsai

IPC: H04L25/14 ,  H04L25/06 ,  H04L25/02

CPC classification number: H04L25/14 ,  H04L25/0202 ,  H04L25/068

Abstract: A de-skew circuit, a de-skew method and a receiver are provided. The de-skew circuit includes N data synchronization circuits and a controller. An nth data synchronization circuit among the N data synchronization circuits includes an nth command detector and an nth buffer. The nth command detector changes an nth command detection signal when an nth input data stream satisfies a single channel condition. The nth buffer stores the nth input data stream in response to a voltage change of the nth command detection signal. The controller receives the nth command detection signal and changes a pop signal when a global channel condition is satisfied. The nth buffer outputs an nth timing-aligned data stream in response to a voltage change of the pop signal.

公开(公告)号：US20230099269A1

公开(公告)日：2023-03-30

申请号：US17565503

申请日：2021-12-30

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Vinod Kumar JAIN ,  Chi-Yeu CHAO

IPC: G06F1/10 ,  G06F1/12 ,  G06F1/08

Abstract: A clock calibration module, a high-speed receiver, and an associated calibration method are provided. The calibration method is applied to the high-speed receiver having the clock calibration module and a sampler. The sampler samples an equalized data signal with a sampler-input clock. The clock calibration module includes multiple clock generation circuits and a clock calibration circuit. Each of the clock generation circuits includes a phase interpolator, a duty cycle corrector, and a phase corrector. In a calibration mode, the phase interpolator interpolates a reference input clock and generates an interpolated clock accordingly. The duty cycle corrector generates a duty cycle corrected clock based on the interpolated clock. The phase corrector generates the sampler-input clock based on the duty cycle corrected clock. The phase interpolator is controlled by a phase interpolator calibration signal, and the phase corrector is controlled by a phase corrector calibration signal.

公开(公告)号：US20220239287A1

公开(公告)日：2022-07-28

申请号：US17722669

申请日：2022-04-18

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Yu-Hao LIU ,  Sheng-Hua CHEN ,  Cheng-Hsing CHIEN

IPC: H03K3/356 ,  H03K3/012

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

公开(公告)号：US11381222B2

公开(公告)日：2022-07-05

申请号：US17178194

申请日：2021-02-17

Applicant: FARADAY TECHNOLOGY CORPORATION ,  Faraday Technology Corp.

Inventor： Ling Chen ,  Andrew Chao ,  Xiao-Dong Fei

IPC: H03K3/012 ,  H03K5/01 ,  H03K5/1252 ,  H03K5/00 ,  H04B1/16 ,  H03K3/037 ,  H03K19/20

Abstract: An apparatus for performing baseline wander correction (BLWC) with the aid of differential wander current sensing includes filters and a correction circuit. The filters are positioned in a front-end circuit of a receiver and coupled to a set of input terminals of the receiver, and filter a set of input signals on the set of input terminals to generate a set of differential signals on a set of secondary terminals, for further usage by the receiver. The correction circuit is positioned in the frontend circuit and electrically connected to the set of input terminals and the set of secondary terminals, and performs BLWC on the set of differential signals according to the set of input signals. In the correction circuit, amplifiers and resistors form a differential wander current sensor to sense differential wander current, and a set of current mirrors generate corresponding baseline wander compensation current to perform BLWC.

公开(公告)号：US20220182055A1

公开(公告)日：2022-06-09

申请号：US17399312

申请日：2021-08-11

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Chih-Hung WU ,  Yu-Chieh MA

IPC: H03K19/003

Abstract: An input/output module electrically coupled between a control circuit and an input/output pin is provided. The input/output module includes a pre-driver and a post-driver. The pre-driver is electrically coupled to the control circuit, and the post-driver is electrically coupled between the pre-driver and the input/output pin. The pre-driver generates a pull-up selection signal and a pull-down selection signal according to an input signal and an enable signal generated by the control circuit. The post-driver sets a voltage level of the input/output pin according to the pull-up and pull-down selection signals. When the enable signal is at a first logic level, the input/output pin has a high impedance. When the enable signal is at a second logic level, the voltage level of the input/output pin changes with a logic level of the input signal, wherein the first logic level and the second logic level are inverted.

公开(公告)号：US20220164136A1

公开(公告)日：2022-05-26

申请号：US16953549

申请日：2020-11-20

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Hong-Yi WU ,  Sivaramakrishnan SUBRAMANIAN ,  Sridhar CHERUKU ,  Ko-Ching CHAO

IPC: G06F3/06 ,  G11C11/4076 ,  G06F13/16

Abstract: A gate signal control circuit of a DDR memory system includes a comparing circuit, a flag generator and a signal generator. The comparing circuit receives a first data strobe signal and a second data strobe signal, and generates an internal data strobe signal. The flag generator receives a physical layer clock signal and a read enable signal, and generates plural flag signals. The signal generator receives the internal data strobe signal and the plural flag signal, and generates a gate signal. When plural read commands are issued, the flag generator sets the flag signals according to the physical layer clock signal and the read enable signal. When a read data is received, the signal generator opens the gate signal according to a preamble, and the signal generator samples the plural flag signals to determine the timing of closing the gate signal.

公开(公告)号：US11342904B1

公开(公告)日：2022-05-24

申请号：US17184640

申请日：2021-02-25

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Yu-Hao Liu ,  Sheng-Hua Chen ,  Cheng-Hsing Chien

IPC: H03K3/012 ,  H03K3/356

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

公开(公告)号：US11044124B1

公开(公告)日：2021-06-22

申请号：US17128266

申请日：2020-12-21

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Prateek Kumar Goyal

IPC: H04L25/03 ,  H04L7/033

Abstract: A dynamic module and a decision feedback equalizer are provided. The decision feedback equalizer includes two dynamic modules, which have symmetric circuits and connections. The dynamic module includes a first domino circuit, a second domino circuit, and a storage circuit. In response to a first previous decision bit and a second previous decision bit, a first multiplexer output and a second multiplexer output are generated. The dynamic module alternatively operates in an evaluation period and a precharge period, depending on a clock signal. In the evaluation period, the first and the second multiplexer outputs are updated by the first domino circuit and the second domino circuit. In the precharge period, the first and the second multiplexer outputs are held by the storage circuit.

公开(公告)号：US10855437B1

公开(公告)日：2020-12-01

申请号：US16583234

申请日：2019-09-25

Applicant: Faraday Technology Corporation ,  Faraday Technology Corp.

Inventor： Ling Chen ,  Andrew Chao ,  Xiao-Dong Fei ,  Wei Liu

IPC: H04L7/033 ,  H03L7/08

Abstract: The present invention provides a clock data recovery apparatus and an operation method thereof. The clock data recovery apparatus includes an equalizer, a phase detector, a charge pump, and an oscillation circuit. The equalizer is configured to equalize raw data to generate equalized data. The phase detector is coupled to the equalizer to receive the equalized data. The phase detector is configured to generate a detection result according to the equalized data. The phase detector performs pattern-filtering on the equalized data to filter out at least one pattern. The charge pump is coupled to the phase detector to receive the detection result. The charge pump is configured to generate a control signal according to the detection result. The oscillation circuit is coupled to the charge pump to receive the control signal. The oscillation circuit is configured to generate a clock signal according to the control signal.

公开(公告)号：US20200303948A1

公开(公告)日：2020-09-24

申请号：US16459680

申请日：2019-07-02

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Chun-Yuan LAI

IPC: H02J9/06

Abstract: A circuit system includes a first power source, a second power source, a first interface circuit, a second interface circuit and an isolation circuit. The first interface circuit is included in a first power domain. The second interface circuit is includes in a second power domain. The bus signal group from the first interface circuit is transmitted to the second interface circuit through the isolation circuit. In a power-saving mode, the bus signal group in a floating state can be effectively isolated by the isolation circuit. If a sudden power interruption event occurs when the circuit system is in the normal working mode, the bus signal group in the floating state is isolated by the isolation circuit. Moreover, the isolation circuit is capable of filtering off the incomplete transaction data, and thus the second interface circuit is not suffered from malfunction.