公开(公告)号：US08121627B2

公开(公告)日：2012-02-21

申请号：US11835205

申请日：2007-08-07

Applicant: Ho-Jun Lee ,  Chul-Yong Jeon

Inventor： Ho-Jun Lee ,  Chul-Yong Jeon

IPC: H04W4/00 ,  H04M1/00

CPC classification number: H04M1/645 ,  H04M1/72566

Abstract: Disclosed are a method and a mobile terminal for outputting an automatic response message informing a caller of a user's (i.e. recipient's) current schedule when the user is unable to answer an incoming call. The method includes receiving an incoming call, determining whether an automatic response key is pressed to output an automatic response message with implementation of the schedule management function, detecting any schedule information corresponding to the current time by reference to a schedule management table when the automatic response key is pressed, and sending a schedule informing message including the detected schedule information to a caller's terminal.

Abstract translation: 公开了一种方法和移动终端，用于在用户不能应答呼入时输出通知呼叫者用户（即接收方）当前时间表的自动应答消息。 该方法包括接收来电，确定是否按照自动响应键输出自动响应消息，并执行日程管理功能，当自动响应时参考时间表管理表，检测与当前时间相对应的任何时间表信息 键，并向呼叫者的终端发送包括检测到的日程信息的调度通知消息。

公开(公告)号：US20120003768A1

公开(公告)日：2012-01-05

申请号：US13231225

申请日：2011-09-13

Applicant: Hong-Kee CHIN ,  Sang-Gab KIM ,  Woong-Kwon KIM ,  Yong-Mo CHOI ,  Seung-Ha CHOI ,  Shin-Il CHOI ,  Ho-Jun LEE ,  Jung-Suk BANG ,  Yu-Gwang JEONG

Inventor： Hong-Kee CHIN ,  Sang-Gab KIM ,  Woong-Kwon KIM ,  Yong-Mo CHOI ,  Seung-Ha CHOI ,  Shin-Il CHOI ,  Ho-Jun LEE ,  Jung-Suk BANG ,  Yu-Gwang JEONG

IPC: H01L33/16

CPC classification number: H01L27/12 ,  H01L27/1248 ,  H01L27/1288

Abstract: A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer.

Abstract translation: 提供一种薄膜晶体管（TFT）基板，其中在接触部分中提供导电材料之间的足够大的接触面积以及制造TFT基板的方法。 TFT基板包括形成在绝缘基板上的栅极互连线，覆盖栅极互连线的栅极绝缘层，布置在栅极绝缘层上的半导体层，包括数据线，源极和漏极的数据互连线 形成在所述半导体层上，形成在所述数据互连线上并暴露所述漏电极的第一钝化层，形成在所述第一钝化膜上的第二钝化层和与所述漏电极电连接的像素电极。 第二钝化层的外侧壁位于第一钝化层的外侧壁的内侧。

公开(公告)号：US20110272703A1

公开(公告)日：2011-11-10

申请号：US13145790

申请日：2009-12-09

Applicant: Ho-Jun Lee ,  Dong-Kun Lee ,  Yong-Jin Kim ,  Doo-Soo Kim

Inventor： Ho-Jun Lee ,  Dong-Kun Lee ,  Yong-Jin Kim ,  Doo-Soo Kim

IPC: H01L29/12 ,  H01L21/20 ,  H01L33/02

CPC classification number: H01L33/007 ,  H01L33/0075 ,  H01L33/10 ,  H01L33/22

Abstract: Disclosed are a semiconductor device, a light emitting device and a method for manufacturing the same. The semiconductor device includes a substrate, a plurality of rods disposed on the substrate, a plurality of particles disposed between the rods and on the substrate, and a first semiconductor layer disposed on the rods. The method for manufacturing the semiconductor device includes preparing a substrate, disposing a plurality of first particles on the substrate, and forming a plurality of rods by etching a portion of the substrate by using the first particles as an etch mask. The semiconductor device effectively reflects in an upward direction light by the above particles, so that light efficiency is improved. The rods are easily formed by using the first particles.

Abstract translation: 公开了一种半导体器件，发光器件及其制造方法。 半导体器件包括衬底，设置在衬底上的多个棒，设置在杆之间和衬底上的多个颗粒以及设置在杆上的第一半导体层。 半导体器件的制造方法包括：准备基板，在基板上配置多个第一粒子，通过使用第一粒子作为蚀刻掩模，蚀刻基板的一部分来形成多个棒。 半导体器件通过上述粒子有效地向上方向反射光，从而提高光效率。 通过使用第一颗粒容易地形成棒。

公开(公告)号：US08044405B2

公开(公告)日：2011-10-25

申请号：US12429388

申请日：2009-04-24

Applicant: Hong-Kee Chin ,  Sang-Gab Kim ,  Woong-Kwon Kim ,  Yong-Mo Choi ,  Seung-Ha Choi ,  Shin-Il Choi ,  Ho-Jun Lee ,  Jung-Suk Bang ,  Yu-Gwang Jeong

Inventor： Hong-Kee Chin ,  Sang-Gab Kim ,  Woong-Kwon Kim ,  Yong-Mo Choi ,  Seung-Ha Choi ,  Shin-Il Choi ,  Ho-Jun Lee ,  Jung-Suk Bang ,  Yu-Gwang Jeong

IPC: H01L29/12 ,  H01L21/336

CPC classification number: H01L27/12 ,  H01L27/1248 ,  H01L27/1288

Abstract: A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer.

Abstract translation: 提供一种薄膜晶体管（TFT）基板，其中在接触部分中提供导电材料之间的足够大的接触面积以及制造TFT基板的方法。 TFT基板包括形成在绝缘基板上的栅极互连线，覆盖栅极互连线的栅极绝缘层，布置在栅极绝缘层上的半导体层，包括数据线，源极和漏极的数据互连线 形成在所述半导体层上，形成在所述数据互连线上并暴露所述漏电极的第一钝化层，形成在所述第一钝化膜上的第二钝化层和与所述漏电极电连接的像素电极。 第二钝化层的外侧壁位于第一钝化层的外侧壁的内侧。

公开(公告)号：US20110095294A1

公开(公告)日：2011-04-28

申请号：US12875228

申请日：2010-09-03

Applicant: Ho-Jun LEE ,  Yeo-Geon YOON ,  Hyoung-Wook LEE ,  Mi-Ae LEE

Inventor： Ho-Jun LEE ,  Yeo-Geon YOON ,  Hyoung-Wook LEE ,  Mi-Ae LEE

IPC: H01L33/00 ,  H01L21/84

CPC classification number: H01L27/124 ,  H01L27/1244 ,  H01L27/1288

Abstract: A thin film transistor array panel includes: an insulation substrate; a gate line disposed on the insulation substrate and including a compensation pattern protruding from the gate line; a first data line and a second data line both intersecting the gate line; a first thin film transistor connected to the gate line and the first data line; a second thin film transistor connected to the gate line and the second data line; and a first pixel electrode and a second pixel electrode connected to the first thin film transistor and the second thin film transistor, respectively. The first pixel electrode and the second pixel electrode share the compensation pattern.

Abstract translation: 薄膜晶体管阵列面板包括：绝缘基板; 栅极线，设置在所述绝缘基板上并且包括从所述栅极线突出的补偿图案; 第一数据线和第二数据线都与所述栅极线相交; 连接到栅极线和第一数据线的第一薄膜晶体管; 连接到栅极线和第二数据线的第二薄膜晶体管; 以及分别连接到第一薄膜晶体管和第二薄膜晶体管的第一像素电极和第二像素电极。 第一像素电极和第二像素电极共享补偿图案。

公开(公告)号：US20110086474A1

公开(公告)日：2011-04-14

申请号：US12729172

申请日：2010-03-22

Applicant: Hong-Kee CHIN ,  Yunjong Yeo ,  Sanggab Kim ,  Junho Song ,  Kyehun Lee ,  Ho-Jun Lee

Inventor： Hong-Kee CHIN ,  Yunjong Yeo ,  Sanggab Kim ,  Junho Song ,  Kyehun Lee ,  Ho-Jun Lee

IPC: H01L21/336

CPC classification number: H01L27/1288 ,  H01L27/1214

Abstract: A method of manufacturing a thin film transistor substrate includes a first process in which a gate line pattern including a gate line and a gate electrode is formed with a first conductive material on a substrate using a first mask, a second process in which a first insulating layer is formed on the substrate and a data line pattern including a data line, a source electrode, and a drain electrode is formed with a second conductive material using a second mask, and a third process in which a second insulating layer is formed on the substrate and a pixel electrode connected to the drain electrode is formed on the second insulating layer with a third conductive material.

Abstract translation: 制造薄膜晶体管基板的方法包括第一工艺，其中包括栅极线和栅电极的栅极线图案使用第一掩模在基板上形成第一导电材料;第二工艺，其中第一绝缘 在衬底上形成层，并且使用第二掩模，用第二导电材料形成包括数据线，源电极和漏电极的数据线图案，以及在第二掩模上形成第二绝缘层的第三工艺 连接到漏极的衬底和像素电极用第三导电材料形成在第二绝缘层上。

公开(公告)号：US20100159652A1

公开(公告)日：2010-06-24

申请号：US12436356

申请日：2009-05-06

Applicant: Woong-Kwon Kim ,  Ho-Jun Lee ,  Hong-Kee Chin ,  Sang-Heon Song ,  Jung-Suk Bank ,  Jun-Ho Song ,  Byeong-Jae Ahn ,  Bae-Heuk Yim

Inventor： Woong-Kwon Kim ,  Ho-Jun Lee ,  Hong-Kee Chin ,  Sang-Heon Song ,  Jung-Suk Bank ,  Jun-Ho Song ,  Byeong-Jae Ahn ,  Bae-Heuk Yim

IPC: H01L21/336

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L27/1255

Abstract: In manufacturing a thin film transistor array substrate, a passivation film is formed over the transistors. A first photoresist pattern is formed over the passivation film, with a first portion partially overlying at least one source/drain electrode of each transistor and overlying each pixel electrode region, and with a second portion thicker than the first portion. The passivation film is patterned using the first photoresist pattern as a mask. The first photoresist pattern's first portion is removed to form a second photoresist pattern which protrudes upward around the pixel electrode regions. A transparent conductive film is formed with recesses in the pixel electrode regions. A masking pattern is formed over the transparent film in each pixel electrode region, the masking pattern's top surface being below a top of the transparent film. The transparent film is patterned using the masking pattern as a mask to form the pixel electrodes.

Abstract translation: 在制造薄膜晶体管阵列基板时，在晶体管上形成钝化膜。 在钝化膜上形成第一光致抗蚀剂图案，其中第一部分部分地覆盖每个晶体管的至少一个源极/漏电极并且覆盖每个像素电极区域，并且具有比第一部分更厚的第二部分。 使用第一光致抗蚀剂图案作为掩模来图案化钝化膜。 去除第一光致抗蚀剂图案的第一部分以形成在像素电极区域周围向上突出的第二光致抗蚀剂图案。 透明导电膜在像素电极区域中形成有凹陷。 在每个像素电极区域中的透明膜上形成掩模图案，掩模图案的顶表面在透明膜的顶部之下。 使用掩模图案作为掩模来对透明膜进行图案化以形成像素电极。

公开(公告)号：US07708832B2

公开(公告)日：2010-05-04

申请号：US12177490

申请日：2008-07-22

Applicant: Yong-Jin Kim ,  Ji-Hoon Kim ,  Dong-Kun Lee ,  Doo-Soo Kim ,  Ho-Jun Lee

Inventor： Yong-Jin Kim ,  Ji-Hoon Kim ,  Dong-Kun Lee ,  Doo-Soo Kim ,  Ho-Jun Lee

IPC: C30B25/00 ,  C30B28/12 ,  H01L21/28

CPC classification number: C30B29/406 ,  C30B25/02 ,  C30B25/18

Abstract: Provided is a method for preparing a substrate for growing gallium nitride and a gallium nitride substrate. The method includes performing thermal cleaning on a surface of a silicon substrate, forming a silicon nitride (Si3N4) micro-mask on the surface of the silicon substrate in an in situ manner, and growing a gallium nitride layer through epitaxial lateral overgrowth (ELO) using an opening in the micro-mask. According to the method, by improving the typical ELO, it is possible to simplify the method for preparing the substrate for growing gallium nitride and the gallium nitride substrate and reduce process cost.

Abstract translation: 提供一种制备用于生长氮化镓和氮化镓衬底的衬底的方法。 该方法包括在硅衬底的表面上进行热清洗，以原位方式在硅衬底的表面上形成氮化硅（Si 3 N 4）微掩模，并通过外延横向过度生长（ELO）生长氮化镓层， 在微面罩中使用开口。 根据该方法，通过改善典型的ELO，可以简化制备用于生长氮化镓和氮化镓衬底的衬底的方法，并降低工艺成本。

公开(公告)号：US20090155986A1

公开(公告)日：2009-06-18

申请号：US12332198

申请日：2008-12-10

Applicant: Ho-Jun Lee ,  Doo-Soo Kim ,  Dong-Kun Lee ,  Yong-Jin Kim

Inventor： Ho-Jun Lee ,  Doo-Soo Kim ,  Dong-Kun Lee ,  Yong-Jin Kim

IPC: H01L21/203

CPC classification number: C30B29/406 ,  C30B25/18

Abstract: The present invention relates to a method for manufacturing a gallium nitride single crystalline substrate, including (a) growing a gallium nitride film on a flat base substrate made of a material having a smaller coefficient of thermal expansion than gallium nitride and cooling the gallium nitride film to bend convex upwards the base substrate and the gallium nitride film and create cracks in the gallium nitride film; (b) growing a gallium nitride single crystalline layer on the crack-created gallium nitride film located on the convex upward base substrate; and (c) cooling a resultant product having the grown gallium nitride single crystalline layer to make the convex upward resultant product flat or bend convex downwards the convex upward resultant product and at the same time to self-split the base substrate and the gallium nitride single crystalline layer from each other at the crack-created gallium nitride film interposed therebetween.

Abstract translation: 本发明涉及一种用于制造氮化镓单晶衬底的方法，包括（a）在具有比氮化镓更小的热膨胀系数的材料制成的平坦基底衬底上生长氮化镓膜并冷却氮化镓膜 使基底和氮化镓膜向上弯曲并在氮化镓膜中产生裂纹; （b）在位于凸起的上方的基底基板上的裂纹产生的氮化镓膜上生长氮化镓单晶层; 和（c）冷却具有生长的氮化镓单晶层的所得产物，以使凸起的上升产物平坦或向上凸起向上凸起的产生产物，同时使基底衬底和氮化镓单层自分裂 在其间形成的裂纹产生的氮化镓膜彼此相互结合。

公开(公告)号：US07170472B2

公开(公告)日：2007-01-30

申请号：US10224592

申请日：2002-08-21

Applicant: Chung Hoo Park ,  Dong Hyun Kim ,  Sung Hyun Lee ,  Young Kee Kim ,  Jeong Eun Heo ,  Joong Hong Shin ,  Ho Jun Lee ,  Eung Kwan Lee

Inventor： Chung Hoo Park ,  Dong Hyun Kim ,  Sung Hyun Lee ,  Young Kee Kim ,  Jeong Eun Heo ,  Joong Hong Shin ,  Ho Jun Lee ,  Eung Kwan Lee

IPC: G09G3/28

CPC classification number: G09G3/296 ,  G09G3/291 ,  G09G3/2927 ,  G09G2310/066 ,  G09G2320/0238 ,  G09G2320/066

Abstract: An apparatus and method for driving a plasma display panel wherein an initializing discharge can be weakened to lower a dark room brightness and an initialization time can be shortened to permit a single scanning. In the apparatus, a sensing device senses an electrical signal with an initialization waveform applied from a voltage source to a display panel. A controlling device controls said electrical signal with an initialization waveform applied from the voltage source to the display panel by the sensed electrical signal.

Abstract translation: 一种用于驱动等离子体显示面板的装置和方法，其中可以削弱初始化放电以降低暗室亮度，并且可以缩短初始化时间以允许单次扫描。 在该装置中，感测装置利用从电压源向显示面板施加的初始化波形来感测电信号。 控制装置通过感测到的电信号将从电压源施加的初始化波形控制到显示面板。