公开(公告)号：US20090052153A1

公开(公告)日：2009-02-26

申请号：US11844397

申请日：2007-08-24

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC: H05K9/00

CPC classification number: H05K9/0022

Abstract: An electromagnetic shielding structure that includes a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate. At least one feed through device is associated with the conductive structure and provides signals to the circuit or circuit device. The method includes forming a shielding structure so that the shielding structure at least one of is at least partially arranged within the substrate and surrounds the circuit or circuit device and associating at least one feed through device with the shielding structure.

Abstract translation: 一种电磁屏蔽结构，其包括围绕并容纳布置在基板上的电路或电路装置的导电结构。 至少一个馈送装置与导电结构相关联，并向电路或电路装置提供信号。 所述方法包括形成屏蔽结构，使得所述屏蔽结构至少部分地至少部分地布置在所述基板内并且围绕所述电路或电路装置并且将至少一个馈送装置与所述屏蔽结构相关联。

公开(公告)号：US20080012091A1

公开(公告)日：2008-01-17

申请号：US11859850

申请日：2007-09-24

Applicant: Hanyi Ding ,  Kai Feng ,  Zhong-Xiang He ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC: H01L27/02 ,  H01L27/00 ,  H01L29/00 ,  H01L29/93

CPC classification number: H03L7/099 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0641 ,  H01L27/08 ,  H01L27/0811 ,  H01L28/10 ,  H01L2924/0002 ,  H03J3/20 ,  H01L2924/00

Abstract: An LC tack structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.

Abstract translation: 一种LC粘结结构。 该结构包括在半导体衬底顶部的一组布线级别，从最靠近衬底的最低配线水平到离衬底最远的最高配线电平彼此堆叠的布线电平; 电感处于最高布线水平，电感器限制在最高布线水平的区域的周边内; 以及形成在基板中的变容二极管，变容二极管完全对准在最高布线水平的区域的周边。 该结构可以另外包括在最低布线电平和最高布线电平之间的布线级别的布线级中的电屏蔽。 或者，电感器包括磁芯和交替的非磁性导电金属线圈和围绕磁芯的磁性线圈。

公开(公告)号：US07288417B2

公开(公告)日：2007-10-30

申请号：US10905480

申请日：2005-01-06

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC: H01L21/00

CPC classification number: H01L23/5227 ,  H01F17/0006 ,  H01F41/046 ,  H01F2019/085 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A mixed-signal chip having a signal transformer located between analog circuitry and digital circuitry. The signal transformer includes a primary winding electrically coupled to the analog circuitry and a secondary winding electrically coupled to the digital circuitry. The primary and secondary windings are magnetically coupled with one another via a magnetic core. The magnetic coupling between the primary and secondary windings inhibits the coupling of electrical noise between the analog and digital circuitries.

Abstract translation: 混合信号芯片，具有位于模拟电路和数字电路之间的信号变压器。 信号变压器包括电耦合到模拟电路的初级绕组和电耦合到数字电路的次级绕组。 初级和次级绕组通过磁芯彼此磁耦合。 初级和次级绕组之间的磁耦合阻碍了模拟和数字电路之间的电气噪声耦合。

公开(公告)号：US20070038968A1

公开(公告)日：2007-02-15

申请号：US11161634

申请日：2005-08-10

Applicant: Florian Braun ,  Hanyi Ding ,  Kai Feng ,  Zhong-Xiang He ,  Howard Landis ,  Xuefeng Liu ,  Geoffrey Woodhouse

Inventor： Florian Braun ,  Hanyi Ding ,  Kai Feng ,  Zhong-Xiang He ,  Howard Landis ,  Xuefeng Liu ,  Geoffrey Woodhouse

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Increase power line noise immunity in an IC is provided by using decoupling capacitor structure in an area of the IC that is typically not used for routing, but filled with unconnected and non-functional metal squares (fills). In one embodiment, a method includes providing a circuit design layout; determining a density of a structure in an area of the circuit design layout; and in response to the density being less than a pre-determined density for the structure in the area, filling in a portion of the area with at least one capacitor structure until a combined density of the structure and the at least one capacitor structure in the area is about equal to the pre-determined density. Power line noise immunity is increased by increasing decoupling capacitance without enlarging the IC's total size by using a (fill) area that would normally be filled with unconnected and non-functional metal shapes.

Abstract translation: 通过在IC的区域中使用去耦电容器结构来提供IC中的电力线噪声抗扰度，该结构通常不用于布线，而是填充有未连接和非功能金属正方形（填充）。 在一个实施例中，一种方法包括提供电路设计布局; 确定电路设计布局区域中结构的密度; 并且响应于所述密度小于所述区域中的结构的预定密度，用至少一个电容器结构填充所述区域的一部分，直到所述结构和所述至少一个电容器结构的组合密度在 面积约等于预定密度。 通过使用通常用非连接和非功能金属形状填充的（填充）区域，通过增加去耦电容而不扩大IC的总尺寸来增加电力线噪声抗扰度。

公开(公告)号：US07071530B1

公开(公告)日：2006-07-04

申请号：US10905934

申请日：2005-01-27

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC: H01L21/762

CPC classification number: H01L21/76264 ,  H01L23/552 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure, comprising: providing a substrate having a buried insulative layer and a heavily doped layer; forming a first trench within the substrate around a protected area; filling the first trench with an insulative material, wherein the first trench filled with the insulative material and the buried insulative layer combine to form a high impedance noise isolation that surrounds the protected area on all sides except one side of the protected area to isolate noise from the protected area; forming a second trench within the substrate around the first trench; and filling the second trench with a conductive material, wherein the second trench filled with the conductive material and the heavily doped layer combine to form a low impedance ground path that surrounds the high impedance noise isolation on all sides except one side of the high impedance noise isolation to isolate noise from the protected area.

Abstract translation: 一种形成半导体结构的方法，包括：提供具有掩埋绝缘层和重掺杂层的衬底; 在保护区域周围形成衬底内的第一沟槽; 用绝缘材料填充第一沟槽，其中填充有绝缘材料的第一沟槽和埋入绝缘层组合形成高阻抗噪声隔离，围绕保护区域的保护区域，除了保护区域的一侧以隔离噪声 保护区; 在所述衬底内围绕所述第一沟槽形成第二沟槽; 以及用导电材料填充所述第二沟槽，其中填充有所述导电材料和所述重掺杂层的所述第二沟槽组合以形成低阻抗接地路径，所述低阻抗接地路径围绕除所述高阻抗噪声的一侧之外的所有侧面上的高阻抗噪声隔离 隔离隔离来自保护区的噪音。

公开(公告)号：US07061359B2

公开(公告)日：2006-06-13

申请号：US10604180

申请日：2003-06-30

Applicant: Hanyi Ding ,  Kai Di Feng ,  Zhong-Xiang He ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai Di Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC: H01F5/00

CPC classification number: H01F41/046 ,  H01F17/0006 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor formed on an integrated circuit chip including one or more inner layers (12) between two or more outer layers (14), inductor metal winding turns (16) included in one or more inner layers (12), and a magnetic material forming the two or more outer layers (14) and the one or more inner layers (12). In one embodiment, the magnetic material is a photoresist paste having magnetic particles. In another embodiment, the magnetic material is a series of magnetic metallic strips (32 and 36) disposed on each of the first and second portions (30 and 34, respectively) of the two or more outer layers (14) and on each of the one or more inner layers (12). The series of magnetic metallic strips on the first and second portions (30, 34) form a grid pattern. Other embodiments include an adjustable controlled compound deposit and control windings with adjustable electrical currents.

Abstract translation: 形成在集成电路芯片上的电感器，其包括在一个或多个内层（12）中包括的两个或多个外层（14），电感器金属绕组匝（16）之间的一个或多个内层（12） 两个或多个外层（14）和一个或多个内层（12）。 在一个实施例中，磁性材料是具有磁性颗粒的光致抗蚀剂浆料。 在另一个实施例中，磁性材料是一系列设置在两个或多个外层（14）的第一和第二部分（30和34）的每一个上的磁性金属条（32和36） 一个或多个内层（12）。 第一和第二部分（30,34）上的一系列磁性金属条形成网格图案。 其他实施例包括具有可调电流的可调控制的化合物沉积和控制绕组。

公开(公告)号：US08898605B2

公开(公告)日：2014-11-25

申请号：US12911327

申请日：2010-10-25

Applicant: Hanyi Ding ,  Guoan Wang ,  Wayne H. Woods, Jr.

Inventor： Hanyi Ding ,  Guoan Wang ,  Wayne H. Woods, Jr.

IPC: G06F17/50 ,  H01P3/08 ,  H01P1/15

CPC classification number: H01P3/08 ,  H01P1/15 ,  Y10T29/49117

Abstract: An on-chip tunable transmission line (t-line), methods of manufacture and design structures are provided. The structure includes a tunable transmission line (t-line) with fixed characteristic impedance comprising functionally-differentiated switches used for inductance and capacitance, respectively.

Abstract translation: 提供片上可调输电线（t线），制造方法和设计结构。 该结构包括具有固定特性阻抗的可调传输线（t线），分别包括用于电感和电容的功能差分开关。

公开(公告)号：US20140062519A1

公开(公告)日：2014-03-06

申请号：US13605170

申请日：2012-09-06

Applicant: Hanyi DING ,  John FERRARIO ,  Barton E. GREEN ,  Richard J. ST. PIERRE

Inventor： Hanyi DING ,  John FERRARIO ,  Barton E. GREEN ,  Richard J. ST. PIERRE

IPC: G01R1/067 ,  H05K13/00

CPC classification number: G01R1/07357 ,  Y10T29/49117

Abstract: A test device including cobra probes and a method of manufacturing is disclosed. The test device includes a conductive upper plate having an upper guide hole and a conductive lower plate having a lower guide hole. The test device also includes a conductive cobra probe disposed between the upper guide hole of the upper plate and the lower guide hole of the lower plate. A dielectric material insulates the cobra probe from the upper plate and the lower plate.

Abstract translation: 公开了一种包括眼镜蛇探头和制造方法的测试装置。 测试装置包括具有上引导孔的导电上板和具有下引导孔的导电下板。 测试装置还包括设置在上板的上引导孔和下板的下引导孔之间的导电眼镜蛇探针。 介电材料将眼镜蛇探头与上板和下板绝缘。

公开(公告)号：US08589832B2

公开(公告)日：2013-11-19

申请号：US11844397

申请日：2007-08-24

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC: G06F17/50

CPC classification number: H05K9/0022

Abstract: An electromagnetic shielding structure that includes a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate. At least one feed through device is associated with the conductive structure and provides signals to the circuit or circuit device. The method includes forming a shielding structure so that the shielding structure at least one of is at least partially arranged within the substrate and surrounds the circuit or circuit device and associating at least one feed through device with the shielding structure.

Abstract translation: 一种电磁屏蔽结构，其包括围绕并容纳布置在基板上的电路或电路装置的导电结构。 至少一个馈送装置与导电结构相关联，并向电路或电路装置提供信号。 所述方法包括形成屏蔽结构，使得所述屏蔽结构至少部分地至少部分地布置在所述基板内并且围绕所述电路或电路装置并且将至少一个馈送装置与所述屏蔽结构相关联。

公开(公告)号：US08519892B2

公开(公告)日：2013-08-27

申请号：US13534350

申请日：2012-06-27

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

IPC: H01Q1/38 ,  H01Q19/10

CPC classification number: H01Q1/2283 ,  H01Q1/40 ,  H01Q9/26 ,  H01Q9/285 ,  H01Q19/108 ,  H01Q19/30

Abstract: A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.

Abstract translation: 提供集成收发器，天线和接收器的半导体芯片。 收发器位于半导体衬底的前侧。 通过基底通孔提供收发器和位于半导体衬底背面的接收器之间的电连接。 连接到收发器的天线位于位于基板正面的电介质层中。 反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。 可以采用贯穿衬底电介质通孔的阵列来降低天线和反射板之间材料的有效介电常数，由此减小毫米波的波长并提高辐射效率。 还提供了用于设计，制造或测试这种半导体芯片的设计的设计结构。