公开(公告)号：US08008659B2

公开(公告)日：2011-08-30

申请号：US11261753

申请日：2005-10-31

Applicant: Yoshifumi Ikenaga ,  Koichi Takeda ,  Masahiro Nomura

Inventor： Yoshifumi Ikenaga ,  Koichi Takeda ,  Masahiro Nomura

IPC: H01L23/58 ,  H01L29/10 ,  H03K3/01

CPC classification number: H03K19/0013 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A substrate bias is controlled such that a leakage current is minimum. A semiconductor integrated circuit device comprises a leakage detecting circuit which detects a leakage current by using leakage detecting MOSFETs, a control circuit which generates a control signal depending on an output from the leakage detecting circuit, a substrate bias generating circuit which changes a substrate bias depending on the control signal, and a controlled circuit including a MOSFET having the same characteristics as that of each of the leakage detecting MOSFETs. The leakage detecting circuit detects a substrate leakage current which includes as the substrate bias becomes deep and a subthreshold leakage current which decreases as the substrate bias becomes deep. A control signal is transmitted to the substrate bias generating circuit such that the substrate bias is made deep when the substrate leakage current is smaller than the subthreshold leakage current and such that the substrate bias is made shallow when the substrate leakage current is larger than the subthreshold leakage current.

Abstract translation: 控制衬底偏置使得漏电流最小。 一种半导体集成电路装置，包括利用泄漏检测用MOSFET检测泄漏电流的漏电检测电路，根据来自漏电检测电路的输出产生控制信号的控制电路，将衬底偏置变化的衬底偏置产生电路 控制信号的控制电路以及具有与各漏电检测用MOSFET相同特性的MOSFET的受控电路。 泄漏检测电路检测衬底偏置变深时包括的衬底漏电流，以及随着衬底偏压变深而减小的亚阈值漏电流。 控制信号被传送到衬底偏置产生电路，使得当衬底漏电流小于亚阈值漏电流时衬底偏压变深，并且当衬底泄漏电流大于次阈值时衬底偏置变浅 漏电流。

公开(公告)号：US07801915B2

公开(公告)日：2010-09-21

申请号：US11528932

申请日：2006-09-27

Applicant: Hiroshi Kanayama ,  Hiroshi Nomiyama ,  Koichi Takeda

Inventor： Hiroshi Kanayama ,  Hiroshi Nomiyama ,  Koichi Takeda

IPC: G06F7/00

CPC classification number: G06F21/62 ,  G06F2221/2141

Abstract: An apparatus which manages confidentiality of information. This apparatus includes: a recording unit operable to record information in association with a history of users having accessed the information, or, with access rights defining users able to access the information; a generating unit operable to generate management information indicating whether the information should be managed confidentially from users not permitted to access the information; a selecting unit operable to select, based on the history or access rights, users able to access the information; and a notifying unit operable to notify the selected users of the generated management information in association with identification information of the information.

Abstract translation: 管理信息机密性的设备。 该装置包括：记录单元，其可操作以与访问该信息的用户的历史相关联地记录信息，或者具有定义能够访问该信息的用户的访问权限; 生成单元，其可操作用于生成管理信息，该管理信息指示是否应该从不允许访问所述信息的用户保密地管理所述信息; 选择单元，其可操作以基于所述历史或访问权限来选择能够访问所述信息的用户; 以及通知单元，其可操作以将所生成的管理信息与所述信息的识别信息相关联地通知所选择的用户。

公开(公告)号：US07774338B2

公开(公告)日：2010-08-10

申请号：US11528045

申请日：2006-09-26

Applicant: Hiroshi Nomiyama ,  Koichi Takeda ,  Taijiroh Tsutsumi

Inventor： Hiroshi Nomiyama ,  Koichi Takeda ,  Taijiroh Tsutsumi

IPC: G06F7/00 ,  G06F17/30

CPC classification number: G06Q40/06

Abstract: A method and apparatus for associating text information with numerical information. A first phrase corresponding to a time period is generated. The first phrase represents a change in first numerical information over the time period. The first numerical information includes time-series data pertaining to a financial index. The text information is retrieved through use of a retrieval condition that includes the first phrase. The first numerical information is retrieved through use of the retrieval condition and the first phrase. The extracted text information and the retrieved first numerical information are outputted in association with each other.

Abstract translation: 一种用于将文本信息与数字信息相关联的方法和装置。 生成与时间段对应的第一短语。 第一个短语表示该时间段内第一个数字信息的变化。 第一数值信息包括与金融指数有关的时间序列数据。 通过使用包括第一短语的检索条件来检索文本信息。 通过使用检索条件和第一个短语来检索第一个数字信息。 提取的文本信息和检索的第一数字信息彼此相关地输出。

公开(公告)号：US07612416B2

公开(公告)日：2009-11-03

申请号：US10575631

申请日：2004-09-29

Applicant: Kiyoshi Takeuchi ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe

Inventor： Kiyoshi Takeuchi ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe

IPC: H01L27/01

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7854 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

Abstract translation: 一种半导体器件，包括：MIS型场效应晶体管，其包括从衬底平面突出的半导体凸起部分，从半导体凸起部分顶部延伸到半导体凸起部分的相对侧面上的栅电极，栅极绝缘膜 存在于栅极电极和半导体凸起部分之间，以及设置在半导体凸起部分中的源极和漏极区域; 设置在包括晶体管的基板上的层间绝缘膜; 以及通过用导体填充形成在所述层间绝缘膜中的沟槽而形成的掩埋导体互连，其中所述掩埋导体布线连接所述半导体凸起部分的所述源极和漏极区域中的一个以及所述层间绝缘膜下方的另一个导电部分 。

公开(公告)号：US20090192230A1

公开(公告)日：2009-07-30

申请号：US10585311

申请日：2005-01-06

Applicant: Koichi Takeda ,  Kenji Matsuda ,  Toshimitsu Terao ,  Tadaaki Inoue ,  Takashi Imagawa ,  Shigeru Masumi

Inventor： Koichi Takeda ,  Kenji Matsuda ,  Toshimitsu Terao ,  Tadaaki Inoue ,  Takashi Imagawa ,  Shigeru Masumi

IPC: A61K31/05 ,  A61K9/107 ,  A61P29/00

CPC classification number: A61K47/40 ,  A61K9/107 ,  A61K31/05

Abstract: The present invention provides a propofol-containing fat emulsion that can be administered with reduced vascular pain without incorporating a local anesthetic such as lidocaine; and a process for producing the same. The fat emulsion comprises 0.1 to 5 w/v % of propofol, 2 to 20 w/v % of an oily component, 0.4 to 10 w/v % of an emulsifier and 0.02 to 0.3 w/v % of at least one compound selected from the group consisting of cyclodextrins, cyclodextrin derivatives and pharmacologically acceptable salts thereof, and is in the form of a fat emulsion.

Abstract translation: 本发明提供了一种含有丙泊酚的脂肪乳剂，其可以在不加入局部麻醉剂如利多卡因的情况下施用减少的血管疼痛; 及其制造方法。 脂肪乳剂包含0.1至5w / v％的异丙酚，2至20w / v％的油性成分，0.4至10w / v％的乳化剂和0.02至0.3w / v％的至少一种选择的化合物 来自由环糊精，环糊精衍生物及其药理学上可接受的盐组成的组，并且是脂肪乳剂的形式。

公开(公告)号：US20090144618A1

公开(公告)日：2009-06-04

申请号：US12333238

申请日：2008-12-11

Applicant: Hiroshi Nomiyama ,  Koichi Takeda ,  Taijiroh Tsutsumi

Inventor： Hiroshi Nomiyama ,  Koichi Takeda ,  Taijiroh Tsutsumi

IPC: G06F17/21

CPC classification number: G06Q40/06

Abstract: A method and apparatus for associating text information with numerical information. A first phrase corresponding to a time period is generated. The first phase represents a change in first numerical information over the time period. The first numerical information includes time-series data pertaining to a financial index. The text information is retrieved through use of a retrieval condition that includes the first phrase. The first numerical information is retrieved through use of the retrieval condition and the first phrase. The extracted text information and the retrieved first numerical information are outputted in association with each other.

Abstract translation: 一种用于将文本信息与数字信息相关联的方法和装置。 生成与时间段对应的第一短语。 第一阶段表示在该时间段内的第一数值信息的变化。 第一数值信息包括与金融指数有关的时间序列数据。 通过使用包括第一短语的检索条件来检索文本信息。 通过使用检索条件和第一个短语来检索第一个数字信息。 提取的文本信息和检索的第一数字信息彼此相关地输出。

公开(公告)号：US20080191791A1

公开(公告)日：2008-08-14

申请号：US11813502

申请日：2006-01-06

Applicant: Masahiro Nomura ,  Koichi Takeda

Inventor： Masahiro Nomura ,  Koichi Takeda

IPC: G05F1/10

CPC classification number: H03K19/0008

Abstract: A semiconductor integrated circuit device includes: a switching current observer for observing a switching current; a leakage current observer for observing a leakage current; a comparator which compares the switching current and the leakage current with each other; a threshold voltage controller for controlling a substrate bias voltage in order to make a ratio of the switching current and the leakage current constant; a delay observer for observing a delay amount; and a power supply voltage controller for controlling a power supply voltage in order to keep the delay amount in a predetermined range. In the semiconductor integrated circuit device, a process which enables the minimization of an operation power is carried out by controlling the threshold voltage to make the ratio of the switching current and the leakage current constant at a given clock frequency and controlling the power supply voltage to guarantee the operating speed.

Abstract translation: 一种半导体集成电路器件，包括：用于观察开关电流的开关电流观察器; 用于观察泄漏电流的漏电流观测器; 将开关电流和漏电流进行比较的比较器; 用于控制衬底偏置电压以使开关电流和漏电流的比率恒定的阈值电压控制器; 用于观察延迟量的延迟观察器; 以及用于控制电源电压以便将延迟量保持在预定范围内的电源电压控制器。 在半导体集成电路器件中，通过控制阈值电压来实现能够最小化操作功率的处理，以使给定时钟频率下的开关电流和漏电流的比率恒定，并将电源电压控制为 保证运行速度。

公开(公告)号：US20080029821A1

公开(公告)日：2008-02-07

申请号：US11632352

申请日：2005-07-04

Applicant: Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

Inventor： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/7851

Abstract: The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a part of the semiconductor substrate, and an insulating film on the shallow substrate flat surface; and the protrusive semiconductor layer of the Fin type FET is formed of a portion protruding from the insulating film of the semiconductor raised portion.

Abstract translation: 本发明涉及一种半导体器件，其包括具有从衬底平面突出的突出半导体层的鳍型场效应晶体管（FET），形成为跨越突出半导体层的栅极电极，栅极电极 所述突出半导体层以及设置在所述突出半导体层中的源极和漏极区域，其中所述半导体器件在半导体衬底上具有具有鳍型FET的元件形成区域，设置在所述半导体衬底上的沟槽，用于将所述元件形成区域 来自另一个元件形成区域，以及沟槽中的元件隔离绝缘膜; 元件形成区域具有通过挖掘到比沟槽的底表面浅的深度而比半导体衬底的上表面更深的深浅的衬底平坦表面，从衬底平坦表面突出并形成的半导体凸起部分 的半导体衬底，以及在浅衬底平面上的绝缘膜; 并且鳍式FET的突出半导体层由从半导体凸起部分的绝缘膜突出的部分形成。

公开(公告)号：US20070257277A1

公开(公告)日：2007-11-08

申请号：US11570025

申请日：2005-05-07

Applicant: Koichi Takeda ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Shigeharu Yamagami ,  Masahiro Nomura ,  Masayasu Tanaka ,  Koichi Terashima ,  Risho Koh ,  Katsuhiko Tanaka

Inventor： Koichi Takeda ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Shigeharu Yamagami ,  Masahiro Nomura ,  Masayasu Tanaka ,  Koichi Terashima ,  Risho Koh ,  Katsuhiko Tanaka

IPC: H01L21/8244 ,  H01L21/82

CPC classification number: H01L27/11 ,  H01L21/84 ,  H01L21/86 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/785

Abstract: A semiconductor device having SRAM cell units each comprising a pair of driving transistors, a pair of load transistors and a pair of access transistors, in which each of the transistors has a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulting film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; a longitudinal direction of each semiconductor layer extends along a first direction; and between the adjacent SRAM cell units in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer in the other transistor which center line extends along the first direction.

Abstract translation: 一种具有SRAM单元单元的半导体器件，每个单元包括一对驱动晶体管，一对负载晶体管和一对存取晶体管，其中每个晶体管具有从衬底平面向上突出的半导体层，相对延伸的栅电极 半导体层的侧面，跨越半导体层的顶部，插入在栅极电极和半导体层之间的栅极绝缘膜，以及形成在半导体层中的一对源极/漏极区域; 每个半导体层的纵向方向沿第一方向延伸; 并且在第一方向上的相邻SRAM单元单元之间，一个对应的晶体管中的半导体层位于另一个晶体管的半导体层的中心线上，该中心线沿第一方向延伸。

公开(公告)号：US07292481B2

公开(公告)日：2007-11-06

申请号：US10570313

申请日：2004-08-27

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C7/10

CPC classification number: G11C11/419

Abstract: There is provided a semiconductor storage device capable of executing a high-speed read operation without increasing a chip area thereof. The semiconductor storage device includes per-bit sensing circuits 103 each connected to a pair of bit lines (BLT, BLN) and a data output circuit 104 connected to the bit lines BLT from the per-bit sensing circuits, for outputting read data. Each of the per-bit sensing circuits 103 includes a pre-charge circuit for setting the bit line pair to a supply voltage VDD when a bit line pair selection signal YS is inactive, a latch circuit for setting the bit line pair to complementary levels (VDD and GND) according to a read signal when the bit line pair selection signal YS and a sensing circuit activation signal SE are active, and a data write circuit connected to a pair of write data lines (WDT, WDN), for setting one of the bit line pair to a second level (GND) according to write data when the bit line pair selection signal is active. The data output circuit 104 includes a logic circuit and an output transistor. The logic circuit outputs a first value when the bit lines are all at a first level (VDD) and outputs a second value when at least one of the bit lines is at the second level. The output transistor outputs read data to a data output line DL based on an output of the logic circuit.

Abstract translation: 提供一种能够在不增加其芯片面积的情况下执行高速读取操作的半导体存储装置。 半导体存储装置包括每位连接到一对位线（BLT，BLN）的每位检测电路103和从每位检测电路连接到位线BLT的数据输出电路104，用于输出读取数据。 每位感测电路103包括用于在位线对选择信号YS无效时将位线对设置为电源电压VDD的预充电电路，用于将位线对设置为互补电平的锁存电路（ VDD和GND），以及与一对写入数据线（WDT，WDN）连接的数据写入电路，用于设置位线对选择信号YS和感测电路激活信号SE之间的读取信号， 当位线对选择信号有效时，根据写入数据，位线对成为第二电平（GND）。 数据输出电路104包括逻辑电路和输出晶体管。 当位线全部处于第一电平（VDD）时，逻辑电路输出第一值，并且当至少一个位线处于第二电平时输出第二值。 输出晶体管基于逻辑电路的输出将读取的数据输出到数据输出线DL。