公开(公告)号：US20070132009A1

公开(公告)日：2007-06-14

申请号：US10575631

申请日：2004-09-29

申请人： Kiyoshi Takeuchi ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe

发明人： Kiyoshi Takeuchi ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe

IPC分类号： H01L29/788

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7854 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

摘要翻译： 一种半导体器件，包括：MIS型场效应晶体管，其包括从衬底平面突出的半导体凸起部分，从半导体凸起部分顶部延伸到半导体凸起部分的相对侧面上的栅电极，栅极绝缘膜 存在于栅极电极和半导体凸起部分之间，以及设置在半导体凸起部分中的源极和漏极区域; 设置在包括晶体管的基板上的层间绝缘膜; 以及通过用导体填充形成在所述层间绝缘膜中的沟槽而形成的掩埋导体互连，其中所述掩埋导体布线连接所述半导体凸起部分的所述源极和漏极区域中的一个以及所述层间绝缘膜下方的另一个导电部分 。

公开(公告)号：US07612416B2

公开(公告)日：2009-11-03

申请号：US10575631

申请日：2004-09-29

申请人： Kiyoshi Takeuchi ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe

发明人： Kiyoshi Takeuchi ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe

IPC分类号： H01L27/01

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7854 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

摘要翻译： 一种半导体器件，包括：MIS型场效应晶体管，其包括从衬底平面突出的半导体凸起部分，从半导体凸起部分顶部延伸到半导体凸起部分的相对侧面上的栅电极，栅极绝缘膜 存在于栅极电极和半导体凸起部分之间，以及设置在半导体凸起部分中的源极和漏极区域; 设置在包括晶体管的基板上的层间绝缘膜; 以及通过用导体填充形成在所述层间绝缘膜中的沟槽而形成的掩埋导体互连，其中所述掩埋导体布线连接所述半导体凸起部分的所述源极和漏极区域中的一个以及所述层间绝缘膜下方的另一个导电部分 。

公开(公告)号：US20080029821A1

公开(公告)日：2008-02-07

申请号：US11632352

申请日：2005-07-04

申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/7851

摘要： The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a part of the semiconductor substrate, and an insulating film on the shallow substrate flat surface; and the protrusive semiconductor layer of the Fin type FET is formed of a portion protruding from the insulating film of the semiconductor raised portion.

摘要翻译： 本发明涉及一种半导体器件，其包括具有从衬底平面突出的突出半导体层的鳍型场效应晶体管（FET），形成为跨越突出半导体层的栅极电极，栅极电极 所述突出半导体层以及设置在所述突出半导体层中的源极和漏极区域，其中所述半导体器件在半导体衬底上具有具有鳍型FET的元件形成区域，设置在所述半导体衬底上的沟槽，用于将所述元件形成区域 来自另一个元件形成区域，以及沟槽中的元件隔离绝缘膜; 元件形成区域具有通过挖掘到比沟槽的底表面浅的深度而比半导体衬底的上表面更深的深浅的衬底平坦表面，从衬底平坦表面突出并形成的半导体凸起部分 的半导体衬底，以及在浅衬底平面上的绝缘膜; 并且鳍式FET的突出半导体层由从半导体凸起部分的绝缘膜突出的部分形成。

公开(公告)号：US20070257277A1

公开(公告)日：2007-11-08

申请号：US11570025

申请日：2005-05-07

申请人： Koichi Takeda ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Shigeharu Yamagami ,  Masahiro Nomura ,  Masayasu Tanaka ,  Koichi Terashima ,  Risho Koh ,  Katsuhiko Tanaka

发明人： Koichi Takeda ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Shigeharu Yamagami ,  Masahiro Nomura ,  Masayasu Tanaka ,  Koichi Terashima ,  Risho Koh ,  Katsuhiko Tanaka

IPC分类号： H01L21/8244 ,  H01L21/82

CPC分类号： H01L27/11 ,  H01L21/84 ,  H01L21/86 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/785

摘要： A semiconductor device having SRAM cell units each comprising a pair of driving transistors, a pair of load transistors and a pair of access transistors, in which each of the transistors has a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulting film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; a longitudinal direction of each semiconductor layer extends along a first direction; and between the adjacent SRAM cell units in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer in the other transistor which center line extends along the first direction.

摘要翻译： 一种具有SRAM单元单元的半导体器件，每个单元包括一对驱动晶体管，一对负载晶体管和一对存取晶体管，其中每个晶体管具有从衬底平面向上突出的半导体层，相对延伸的栅电极 半导体层的侧面，跨越半导体层的顶部，插入在栅极电极和半导体层之间的栅极绝缘膜，以及形成在半导体层中的一对源极/漏极区域; 每个半导体层的纵向方向沿第一方向延伸; 并且在第一方向上的相邻SRAM单元单元之间，一个对应的晶体管中的半导体层位于另一个晶体管的半导体层的中心线上，该中心线沿第一方向延伸。

公开(公告)号：US20090014795A1

公开(公告)日：2009-01-15

申请号：US11658564

申请日：2005-07-14

申请人： Risho Koh ,  Katsuhiko Tanaka ,  Shigeharu Yamagami ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda

发明人： Risho Koh ,  Katsuhiko Tanaka ,  Shigeharu Yamagami ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A π gate FinFET structure having reduced variations in off-current and parasitic capacitance and a method for production thereof are provided. The structure of an element is improved so that an off-current suppressing capability can be exhibited more strongly. A field effect transistor, wherein a first insulating film and a semiconductor region are provided so as to protrude upward with respect to the flat surface of a base, the field effect transistor has a gate electrode, a gate insulating film and a source/drain region, and a channel is formed at least on the side surface of the semiconductor region, wherein that the first insulating film is provided on an etch stopper layer composed of a material having an etching rate lower than at least the lowermost layer of the first insulating film for etching under a predetermined condition.

摘要翻译： 提供了一种具有减小的截止电流和寄生电容的变化的p型门FinFET结构及其制造方法。 改善了元件的结构，使得能够更强烈地显示出截止电流的能力。 一种场效应晶体管，其中第一绝缘膜和半导体区域设置成相对于基底的平坦表面向上突出，所述场效应晶体管具有栅极电极，栅极绝缘膜和源极/漏极区域 并且至少在所述半导体区域的侧表面上形成沟道，其中所述第一绝缘膜设置在由蚀刻速率低于所述第一绝缘膜的最下层的蚀刻速率的材料构成的蚀刻停止层上 用于在预定条件下蚀刻。

公开(公告)号：US20070187682A1

公开(公告)日：2007-08-16

申请号：US10569451

申请日：2004-08-27

申请人： Kiyoshi Takeuchi ,  Koji Watanabe ,  Koichi Terashima ,  Atsushi Ogura ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka ,  Shigeharu Yamagami ,  Hitoshi Wakabayashi

发明人： Kiyoshi Takeuchi ,  Koji Watanabe ,  Koichi Terashima ,  Atsushi Ogura ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka ,  Shigeharu Yamagami ,  Hitoshi Wakabayashi

IPC分类号： H01L29/04

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7854

摘要： There is provided a semiconductor device comprising an n-type and a p-type field effect transistors, meeting the conditions that in terms of a crystal orientation of the protruding semiconductor region constituting the n-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {100} plane substantially orthogonal to the {100} plane, and that in terms of a crystal orientation of the protruding semiconductor region constituting the p-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {110} plane substantially orthogonal to the {100} plane.

摘要翻译： 提供一种包括n型和p型场效应晶体管的半导体器件，满足以下条件：就组成n型场效应晶体管的突出半导体区域的晶体取向而言，其平行于衬底的平面 基本上是{100}面，其侧面是与{100}面大致正交的{100}面，就构成p型场效应晶体管的突出半导体区域的晶体取向而言，其平面 与基板平行的基本上是{100}平面，其侧面是与{100}平面基本正交的{110}平面。

公开(公告)号：US07719043B2

公开(公告)日：2010-05-18

申请号：US11632352

申请日：2005-07-04

申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/7851

摘要： The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a part of the semiconductor substrate, and an insulating film on the shallow substrate flat surface; and the protrusive semiconductor layer of the Fin type FET is formed of a portion protruding from the insulating film of the semiconductor raised portion.

摘要翻译： 本发明涉及一种半导体器件，其包括具有从衬底平面突出的突出半导体层的鳍型场效应晶体管（FET），形成为跨越突出半导体层的栅极电极，栅极电极 所述突出半导体层以及设置在所述突出半导体层中的源极和漏极区域，其中所述半导体器件在半导体衬底上具有具有鳍型FET的元件形成区域，设置在所述半导体衬底上的沟槽，用于将所述元件形成区域 来自另一个元件形成区域，以及沟槽中的元件隔离绝缘膜; 元件形成区域具有通过挖掘到比沟槽的底表面浅的深度而比半导体衬底的上表面更深的深浅的衬底平坦表面，从衬底平坦表面突出并形成的半导体凸起部分 的半导体衬底，以及在浅衬底平面上的绝缘膜; 并且鳍式FET的突出半导体层由从半导体凸起部分的绝缘膜突出的部分形成。

公开(公告)号：US07701018B2

公开(公告)日：2010-04-20

申请号：US10593300

申请日：2005-03-22

申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

IPC分类号： H01L27/088

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681 ,  H01L2029/7858

摘要： A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.

摘要翻译： 一种包括第一半导体区域和第二半导体区域的半导体器件，（a）其中场效应晶体管由包括从衬底向上突出的至少一个半导体层的第一半导体区域，栅电极， 通过绝缘膜形成，使得栅电极跨越设置在栅电极两侧的半导体层中的半导体层和源极/漏极区，由此沟道区是 形成在所述半导体层的至少两侧，（b），其中所述第二半导体区域包括从所述衬底向上突出的半导体层，并且至少相对于与沟道垂直的方向的两端处的所述第一半导体区域相对 电流方向和面对第一半导体区域的半导体层的侧表面平行于沟道电流方向。

公开(公告)号：US07830703B2

公开(公告)日：2010-11-09

申请号：US11570037

申请日：2005-05-25

申请人： Koichi Takeda ,  Masahiro Nomura ,  Kiyoshi Takeuchi ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Risho Koh ,  Koichi Terashima ,  Katsuhiko Tanaka ,  Masayasu Tanaka

发明人： Koichi Takeda ,  Masahiro Nomura ,  Kiyoshi Takeuchi ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Risho Koh ,  Koichi Terashima ,  Katsuhiko Tanaka ,  Masayasu Tanaka

IPC分类号： G11C11/00

CPC分类号： H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/785 ,  Y10S257/903

摘要： A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.

摘要翻译： 一种具有SRAM单元单元的半导体器件，每个SRAM单元包括一对第一驱动晶体管和第二驱动晶体管，一对第一负载晶体管和第二负载晶体管，以及一对第一存取晶体管和第二存取晶体管，其中 每个晶体管包括从衬底平面向上突出的半导体层，在半导体层的相对侧上延伸以跨越半导体层的顶部的栅极电极，插入在栅极电极和半导体之间的栅极绝缘膜 层，以及形成在半导体层中的一对源极/漏极区域; 并且第一和第二驱动晶体管的沟道宽度均大于至少任一个负载晶体管或每个存取晶体管的沟道宽度。

公开(公告)号：US20080251849A1

公开(公告)日：2008-10-16

申请号：US10593300

申请日：2005-03-22

申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681 ,  H01L2029/7858

摘要： A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.

摘要翻译： 一种包括第一半导体区域和第二半导体区域的半导体器件，（a）其中场效应晶体管由包括从衬底向上突出的至少一个半导体层的第一半导体区域，栅电极， 通过绝缘膜形成，使得栅电极跨越设置在栅电极两侧的半导体层中的半导体层和源极/漏极区，由此沟道区是 形成在所述半导体层的至少两侧，（b），其中所述第二半导体区域包括从所述衬底向上突出的半导体层，并且至少相对于与沟道垂直的方向的两端处的所述第一半导体区域相对 电流方向和面对第一半导体区域的半导体层的侧表面平行于沟道电流方向。