公开(公告)号：US07612416B2

公开(公告)日：2009-11-03

申请号：US10575631

申请日：2004-09-29

申请人： Kiyoshi Takeuchi ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe

发明人： Kiyoshi Takeuchi ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe

IPC分类号： H01L27/01

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7854 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

摘要翻译： 一种半导体器件，包括：MIS型场效应晶体管，其包括从衬底平面突出的半导体凸起部分，从半导体凸起部分顶部延伸到半导体凸起部分的相对侧面上的栅电极，栅极绝缘膜 存在于栅极电极和半导体凸起部分之间，以及设置在半导体凸起部分中的源极和漏极区域; 设置在包括晶体管的基板上的层间绝缘膜; 以及通过用导体填充形成在所述层间绝缘膜中的沟槽而形成的掩埋导体互连，其中所述掩埋导体布线连接所述半导体凸起部分的所述源极和漏极区域中的一个以及所述层间绝缘膜下方的另一个导电部分 。

公开(公告)号：US20070187682A1

公开(公告)日：2007-08-16

申请号：US10569451

申请日：2004-08-27

申请人： Kiyoshi Takeuchi ,  Koji Watanabe ,  Koichi Terashima ,  Atsushi Ogura ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka ,  Shigeharu Yamagami ,  Hitoshi Wakabayashi

发明人： Kiyoshi Takeuchi ,  Koji Watanabe ,  Koichi Terashima ,  Atsushi Ogura ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka ,  Shigeharu Yamagami ,  Hitoshi Wakabayashi

IPC分类号： H01L29/04

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7854

摘要： There is provided a semiconductor device comprising an n-type and a p-type field effect transistors, meeting the conditions that in terms of a crystal orientation of the protruding semiconductor region constituting the n-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {100} plane substantially orthogonal to the {100} plane, and that in terms of a crystal orientation of the protruding semiconductor region constituting the p-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {110} plane substantially orthogonal to the {100} plane.

摘要翻译： 提供一种包括n型和p型场效应晶体管的半导体器件，满足以下条件：就组成n型场效应晶体管的突出半导体区域的晶体取向而言，其平行于衬底的平面 基本上是{100}面，其侧面是与{100}面大致正交的{100}面，就构成p型场效应晶体管的突出半导体区域的晶体取向而言，其平面 与基板平行的基本上是{100}平面，其侧面是与{100}平面基本正交的{110}平面。

公开(公告)号：US07701018B2

公开(公告)日：2010-04-20

申请号：US10593300

申请日：2005-03-22

申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

IPC分类号： H01L27/088

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681 ,  H01L2029/7858

摘要： A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.

摘要翻译： 一种包括第一半导体区域和第二半导体区域的半导体器件，（a）其中场效应晶体管由包括从衬底向上突出的至少一个半导体层的第一半导体区域，栅电极， 通过绝缘膜形成，使得栅电极跨越设置在栅电极两侧的半导体层中的半导体层和源极/漏极区，由此沟道区是 形成在所述半导体层的至少两侧，（b），其中所述第二半导体区域包括从所述衬底向上突出的半导体层，并且至少相对于与沟道垂直的方向的两端处的所述第一半导体区域相对 电流方向和面对第一半导体区域的半导体层的侧表面平行于沟道电流方向。

公开(公告)号：US20070132009A1

公开(公告)日：2007-06-14

申请号：US10575631

申请日：2004-09-29

申请人： Kiyoshi Takeuchi ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe

发明人： Kiyoshi Takeuchi ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe

IPC分类号： H01L29/788

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7854 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

摘要翻译： 一种半导体器件，包括：MIS型场效应晶体管，其包括从衬底平面突出的半导体凸起部分，从半导体凸起部分顶部延伸到半导体凸起部分的相对侧面上的栅电极，栅极绝缘膜 存在于栅极电极和半导体凸起部分之间，以及设置在半导体凸起部分中的源极和漏极区域; 设置在包括晶体管的基板上的层间绝缘膜; 以及通过用导体填充形成在所述层间绝缘膜中的沟槽而形成的掩埋导体互连，其中所述掩埋导体布线连接所述半导体凸起部分的所述源极和漏极区域中的一个以及所述层间绝缘膜下方的另一个导电部分 。

公开(公告)号：US20080251849A1

公开(公告)日：2008-10-16

申请号：US10593300

申请日：2005-03-22

申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681 ,  H01L2029/7858

摘要： A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.

摘要翻译： 一种包括第一半导体区域和第二半导体区域的半导体器件，（a）其中场效应晶体管由包括从衬底向上突出的至少一个半导体层的第一半导体区域，栅电极， 通过绝缘膜形成，使得栅电极跨越设置在栅电极两侧的半导体层中的半导体层和源极/漏极区，由此沟道区是 形成在所述半导体层的至少两侧，（b），其中所述第二半导体区域包括从所述衬底向上突出的半导体层，并且至少相对于与沟道垂直的方向的两端处的所述第一半导体区域相对 电流方向和面对第一半导体区域的半导体层的侧表面平行于沟道电流方向。

公开(公告)号：US20070075372A1

公开(公告)日：2007-04-05

申请号：US10576412

申请日：2004-10-19

申请人： Koichi Terashima ,  Kiyoshi Takeuchi ,  shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Atsushi Ogura ,  Koji Watanabe ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka

发明人： Koichi Terashima ,  Kiyoshi Takeuchi ,  shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Atsushi Ogura ,  Koji Watanabe ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka

IPC分类号： H01L23/62

CPC分类号： H01L29/7853 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device wherein at least the largest width of a source/drain region is larger than the width of a semiconductor region and the source/drain region has a slope having a width continuously increasing from the uppermost side to the substrate side, and a silicide film is formed in the surface of the slope.

摘要翻译： 提供了一种半导体器件，其中源极/漏极区域的至少最大宽度大于半导体区域的宽度，并且源极/漏极区域具有从最上侧到衬底侧的宽度连续增加的斜率， 并且在斜面的表面中形成硅化物膜。

公开(公告)号：US06933569B2

公开(公告)日：2005-08-23

申请号：US10668349

申请日：2003-09-24

申请人： Risho Koh ,  Shigeharu Yamagami ,  Jong-wook Lee ,  Hitoshi Wakabayashi ,  Yukishige Saito ,  Atsushi Ogura ,  Mitsuru Narihiro ,  Kohichi Arai ,  Hisashi Takemura ,  Tohru Mogami ,  Toyoji Yamamoto ,  Yukinori Ochiai

发明人： Risho Koh ,  Shigeharu Yamagami ,  Jong-wook Lee ,  Hitoshi Wakabayashi ,  Yukishige Saito ,  Atsushi Ogura ,  Mitsuru Narihiro ,  Kohichi Arai ,  Hisashi Takemura ,  Tohru Mogami ,  Toyoji Yamamoto ,  Yukinori Ochiai

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L21/01

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78615 ,  H01L29/78621

摘要： A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.

摘要翻译： 半导体器件包括形成在绝缘体上的半导体层，形成在半导体层上的栅极绝缘膜，形成在栅极绝缘膜上并沿第一方向延伸的栅电极，在两侧的半导体层中形成的源/漏区 所述半导体层中的主体接触区域，其中比所述栅极绝缘膜更厚的场绝缘膜介于所述半导体层和所述栅电极的延伸部分之间的部分隔离区域，以及完全隔离区域 去除绝缘体上的半导体层。 完全隔离区域形成为与平行于源极/漏极区域的第一方向的一侧的至少一部分接触。

公开(公告)号：US06919563B2

公开(公告)日：2005-07-19

申请号：US10649664

申请日：2003-08-28

申请人： Akira Uedono ,  Atsushi Ogura

发明人： Akira Uedono ,  Atsushi Ogura

IPC分类号： G01N23/225 ,  G01N23/00 ,  G01Q30/08 ,  G01T1/172 ,  G21K1/00 ,  G21K1/10 ,  G21K5/04 ,  H01J37/26

CPC分类号： G01T1/172

摘要： Disclosed is a defect evaluation apparatus comprising a source section having a source for generating positrons and a moderator for decelerating the positrons, a sample holding section for holding a sample to be measured, a transfer section for transferring the positrons from the source section to the sample holding section, and detection means for detecting γ rays emitted from the sample being measured, characterized in that the apparatus further comprises heating means for heating the moderator in a position where there is a possibility of the source being thermally damaged if there is no protection means mentioned below in the source section, and protection means for protecting the source from the heating means and heated moderator when the moderator is being heated using the heating means.

摘要翻译： 公开了一种缺陷评估装置，包括：源部分，具有用于产生正电子的源和用于使正电子减速的调节剂;用于保持待测样品的样品保持部分;用于将正电子从源部分转移到样品的转移部分; 保持部，以及检测装置，用于检测被测试样品发射的γ射线，其特征在于，所述装置还包括加热装置，用于在没有保护装置的情况下，在可能发生源受热损坏的位置加热调节剂 以及保护装置，用于当使用加热装置加热调节剂时，保护来自加热装置和加热的慢化剂的源。

公开(公告)号：US6074928A

公开(公告)日：2000-06-13

申请号：US23132

申请日：1998-02-12

申请人： Atsushi Ogura

发明人： Atsushi Ogura

IPC分类号： H01L21/265 ,  H01L21/02 ,  H01L21/762 ,  H01L27/12 ,  H01L21/76

CPC分类号： H01L21/76243

摘要： An oxygen ion is implanted into a silicon substrate at a dose of 3.times.10.sup.17 (cm.sup.-2) or lower. Then, the silicon substrate is heated at 1250.degree. C. or lower for 40 minute or longer. And the silicon substrate is heated at 1300.degree. C. or higher in an inert gas atmosphere. Further, the silicon substrate is heated at 1300.degree. C. or higher in an atmosphere containing an oxygen gas in an amount of 1% by volume or more.

摘要翻译： 将氧离子以3×10 17（cm -2）以下的剂量注入到硅衬底中。 然后，将硅衬底在1250℃或更低温度下加热40分钟以上。 并且在惰性气体气氛中将硅衬底加热至1300℃或更高。 此外，在含有1体积％以上的氧气的气氛中，将硅衬底加热至1300℃以上。

公开(公告)号：US5888297A

公开(公告)日：1999-03-30

申请号：US570232

申请日：1995-12-11

申请人： Atsushi Ogura

发明人： Atsushi Ogura

IPC分类号： H01L21/20 ,  C30B31/22 ,  C30B33/00 ,  H01L21/02 ,  H01L21/265 ,  H01L21/322 ,  H01L27/12 ,  C30B25/02

CPC分类号： C30B29/06 ,  C30B31/22 ,  C30B33/00

摘要： The invention provides a method of fabricating an SOI substrate including the steps of introducing crystal defects at a desired depth in a silicon substrate, and thereafter, implanting oxygen or nitrogen ions into the silicon substrate, and thermally annealing the silicon substrate. The method of the present invention makes it possible to fabricate an SOI substrate with fewer crystal defects and lower fabrication cost than is possible according to the prior art.

摘要翻译： 本发明提供一种制造SOI衬底的方法，包括以下步骤：在硅衬底中以期望的深度引入晶体缺陷，然后将氧或氮离子注入到硅衬底中，并对硅衬底进行热退火。 与现有技术相比，本发明的方法可以制造出具有较少晶体缺陷和较低制造成本的SOI衬底。