公开(公告)号：US07719043B2

公开(公告)日：2010-05-18

申请号：US11632352

申请日：2005-07-04

申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/7851

摘要： The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a part of the semiconductor substrate, and an insulating film on the shallow substrate flat surface; and the protrusive semiconductor layer of the Fin type FET is formed of a portion protruding from the insulating film of the semiconductor raised portion.

摘要翻译： 本发明涉及一种半导体器件，其包括具有从衬底平面突出的突出半导体层的鳍型场效应晶体管（FET），形成为跨越突出半导体层的栅极电极，栅极电极 所述突出半导体层以及设置在所述突出半导体层中的源极和漏极区域，其中所述半导体器件在半导体衬底上具有具有鳍型FET的元件形成区域，设置在所述半导体衬底上的沟槽，用于将所述元件形成区域 来自另一个元件形成区域，以及沟槽中的元件隔离绝缘膜; 元件形成区域具有通过挖掘到比沟槽的底表面浅的深度而比半导体衬底的上表面更深的深浅的衬底平坦表面，从衬底平坦表面突出并形成的半导体凸起部分 的半导体衬底，以及在浅衬底平面上的绝缘膜; 并且鳍式FET的突出半导体层由从半导体凸起部分的绝缘膜突出的部分形成。

公开(公告)号：US20080029821A1

公开(公告)日：2008-02-07

申请号：US11632352

申请日：2005-07-04

申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Risho Koh ,  Kiyoshi Takeuchi ,  Masahiro Nomura ,  Koichi Takeda ,  Koichi Terashima ,  Masayasu Tanaka ,  Katsuhiko Tanaka

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/7851

摘要： The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a part of the semiconductor substrate, and an insulating film on the shallow substrate flat surface; and the protrusive semiconductor layer of the Fin type FET is formed of a portion protruding from the insulating film of the semiconductor raised portion.

摘要翻译： 本发明涉及一种半导体器件，其包括具有从衬底平面突出的突出半导体层的鳍型场效应晶体管（FET），形成为跨越突出半导体层的栅极电极，栅极电极 所述突出半导体层以及设置在所述突出半导体层中的源极和漏极区域，其中所述半导体器件在半导体衬底上具有具有鳍型FET的元件形成区域，设置在所述半导体衬底上的沟槽，用于将所述元件形成区域 来自另一个元件形成区域，以及沟槽中的元件隔离绝缘膜; 元件形成区域具有通过挖掘到比沟槽的底表面浅的深度而比半导体衬底的上表面更深的深浅的衬底平坦表面，从衬底平坦表面突出并形成的半导体凸起部分 的半导体衬底，以及在浅衬底平面上的绝缘膜; 并且鳍式FET的突出半导体层由从半导体凸起部分的绝缘膜突出的部分形成。

公开(公告)号：US20070257277A1

公开(公告)日：2007-11-08

申请号：US11570025

申请日：2005-05-07

申请人： Koichi Takeda ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Shigeharu Yamagami ,  Masahiro Nomura ,  Masayasu Tanaka ,  Koichi Terashima ,  Risho Koh ,  Katsuhiko Tanaka

发明人： Koichi Takeda ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Shigeharu Yamagami ,  Masahiro Nomura ,  Masayasu Tanaka ,  Koichi Terashima ,  Risho Koh ,  Katsuhiko Tanaka

IPC分类号： H01L21/8244 ,  H01L21/82

CPC分类号： H01L27/11 ,  H01L21/84 ,  H01L21/86 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/785

摘要： A semiconductor device having SRAM cell units each comprising a pair of driving transistors, a pair of load transistors and a pair of access transistors, in which each of the transistors has a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulting film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; a longitudinal direction of each semiconductor layer extends along a first direction; and between the adjacent SRAM cell units in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer in the other transistor which center line extends along the first direction.

摘要翻译： 一种具有SRAM单元单元的半导体器件，每个单元包括一对驱动晶体管，一对负载晶体管和一对存取晶体管，其中每个晶体管具有从衬底平面向上突出的半导体层，相对延伸的栅电极 半导体层的侧面，跨越半导体层的顶部，插入在栅极电极和半导体层之间的栅极绝缘膜，以及形成在半导体层中的一对源极/漏极区域; 每个半导体层的纵向方向沿第一方向延伸; 并且在第一方向上的相邻SRAM单元单元之间，一个对应的晶体管中的半导体层位于另一个晶体管的半导体层的中心线上，该中心线沿第一方向延伸。

公开(公告)号：US20090014795A1

公开(公告)日：2009-01-15

申请号：US11658564

申请日：2005-07-14

申请人： Risho Koh ,  Katsuhiko Tanaka ,  Shigeharu Yamagami ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda

发明人： Risho Koh ,  Katsuhiko Tanaka ,  Shigeharu Yamagami ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A π gate FinFET structure having reduced variations in off-current and parasitic capacitance and a method for production thereof are provided. The structure of an element is improved so that an off-current suppressing capability can be exhibited more strongly. A field effect transistor, wherein a first insulating film and a semiconductor region are provided so as to protrude upward with respect to the flat surface of a base, the field effect transistor has a gate electrode, a gate insulating film and a source/drain region, and a channel is formed at least on the side surface of the semiconductor region, wherein that the first insulating film is provided on an etch stopper layer composed of a material having an etching rate lower than at least the lowermost layer of the first insulating film for etching under a predetermined condition.

摘要翻译： 提供了一种具有减小的截止电流和寄生电容的变化的p型门FinFET结构及其制造方法。 改善了元件的结构，使得能够更强烈地显示出截止电流的能力。 一种场效应晶体管，其中第一绝缘膜和半导体区域设置成相对于基底的平坦表面向上突出，所述场效应晶体管具有栅极电极，栅极绝缘膜和源极/漏极区域 并且至少在所述半导体区域的侧表面上形成沟道，其中所述第一绝缘膜设置在由蚀刻速率低于所述第一绝缘膜的最下层的蚀刻速率的材料构成的蚀刻停止层上 用于在预定条件下蚀刻。

公开(公告)号：US07830703B2

公开(公告)日：2010-11-09

申请号：US11570037

申请日：2005-05-25

申请人： Koichi Takeda ,  Masahiro Nomura ,  Kiyoshi Takeuchi ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Risho Koh ,  Koichi Terashima ,  Katsuhiko Tanaka ,  Masayasu Tanaka

发明人： Koichi Takeda ,  Masahiro Nomura ,  Kiyoshi Takeuchi ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Risho Koh ,  Koichi Terashima ,  Katsuhiko Tanaka ,  Masayasu Tanaka

IPC分类号： G11C11/00

CPC分类号： H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/785 ,  Y10S257/903

摘要： A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.

摘要翻译： 一种具有SRAM单元单元的半导体器件，每个SRAM单元包括一对第一驱动晶体管和第二驱动晶体管，一对第一负载晶体管和第二负载晶体管，以及一对第一存取晶体管和第二存取晶体管，其中 每个晶体管包括从衬底平面向上突出的半导体层，在半导体层的相对侧上延伸以跨越半导体层的顶部的栅极电极，插入在栅极电极和半导体之间的栅极绝缘膜 层，以及形成在半导体层中的一对源极/漏极区域; 并且第一和第二驱动晶体管的沟道宽度均大于至少任一个负载晶体管或每个存取晶体管的沟道宽度。

公开(公告)号：US20080079077A1

公开(公告)日：2008-04-03

申请号：US11570037

申请日：2005-05-25

申请人： Koichi Takeda ,  Masahiro Nomura ,  Kiyoshi Takeuchi ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Risho Koh ,  Koichi Terashima ,  Katsuhiko Tanaka ,  Masayasu Tanaka

发明人： Koichi Takeda ,  Masahiro Nomura ,  Kiyoshi Takeuchi ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Risho Koh ,  Koichi Terashima ,  Katsuhiko Tanaka ,  Masayasu Tanaka

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/785 ,  Y10S257/903

摘要： A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.

摘要翻译： 一种具有SRAM单元单元的半导体器件，每个SRAM单元包括一对第一驱动晶体管和第二驱动晶体管，一对第一负载晶体管和第二负载晶体管，以及一对第一存取晶体管和第二存取晶体管，其中 每个晶体管包括从衬底平面向上突出的半导体层，在半导体层的相对侧上延伸以跨越半导体层的顶部的栅极电极，插入在栅极电极和半导体之间的栅极绝缘膜 层，以及形成在半导体层中的一对源极/漏极区域; 并且第一和第二驱动晶体管的沟道宽度均大于至少任一个负载晶体管或每个存取晶体管的沟道宽度。

公开(公告)号：US06933569B2

公开(公告)日：2005-08-23

申请号：US10668349

申请日：2003-09-24

申请人： Risho Koh ,  Shigeharu Yamagami ,  Jong-wook Lee ,  Hitoshi Wakabayashi ,  Yukishige Saito ,  Atsushi Ogura ,  Mitsuru Narihiro ,  Kohichi Arai ,  Hisashi Takemura ,  Tohru Mogami ,  Toyoji Yamamoto ,  Yukinori Ochiai

发明人： Risho Koh ,  Shigeharu Yamagami ,  Jong-wook Lee ,  Hitoshi Wakabayashi ,  Yukishige Saito ,  Atsushi Ogura ,  Mitsuru Narihiro ,  Kohichi Arai ,  Hisashi Takemura ,  Tohru Mogami ,  Toyoji Yamamoto ,  Yukinori Ochiai

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L21/01

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78615 ,  H01L29/78621

摘要： A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.

摘要翻译： 半导体器件包括形成在绝缘体上的半导体层，形成在半导体层上的栅极绝缘膜，形成在栅极绝缘膜上并沿第一方向延伸的栅电极，在两侧的半导体层中形成的源/漏区 所述半导体层中的主体接触区域，其中比所述栅极绝缘膜更厚的场绝缘膜介于所述半导体层和所述栅电极的延伸部分之间的部分隔离区域，以及完全隔离区域 去除绝缘体上的半导体层。 完全隔离区域形成为与平行于源极/漏极区域的第一方向的一侧的至少一部分接触。

公开(公告)号：US20070158700A1

公开(公告)日：2007-07-12

申请号：US10587845

申请日：2005-01-28

申请人： Risho Koh ,  Katsuhiko Tanaka ,  Kiyoshi Takeuchi

发明人： Risho Koh ,  Katsuhiko Tanaka ,  Kiyoshi Takeuchi

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7854 ,  H01L29/78609

摘要： A field effect transistor comprising: a semiconductor layer projecting from the plane of a base; a gate electrode provided on opposite side surfaces of the semiconductor layer; a gate insulating film interposed between the gate electrode and the side surface of the semiconductor layer; and source/drain regions where a first conductivity type impurity is introduced, wherein the semiconductor layer has a channel forming region in a portion sandwiched between the source/drain regions, and has in the upper part of the semiconductor layer in the channel forming region a channel impurity concentration adjusting region of which the concentration of a second conductivity type impurity is higher than that in the lower part of the semiconductor layer, and in the channel impurity concentration adjusting region, a channel is formed in a side surface portion facing the gate insulating film of the semiconductor layer in the channel impurity concentration adjusting region in a state of operation in which a signal voltage is applied to the gate electrode.

摘要翻译： 一种场效应晶体管，包括：从基底的平面突出的半导体层; 设置在所述半导体层的相对侧表面上的栅电极; 介于栅电极和半导体层的侧表面之间的栅极绝缘膜; 以及引入第一导电型杂质的源极/漏极区域，其中半导体层在夹在源极/漏极区域之间的部分中具有沟道形成区域，并且在沟道形成区域a中的半导体层的上部 沟道杂质浓度调整区域，其中第二导电类型杂质的浓度高于半导体层的下部，并且在沟道杂质浓度调节区域中，在面向栅极绝缘体的侧表面部分中形成沟道 在对栅电极施加信号电压的工作状态下的沟道杂质浓度调整区域中的半导体层的膜。

公开(公告)号：US07211517B2

公开(公告)日：2007-05-01

申请号：US10476978

申请日：2002-09-05

申请人： Yukishige Saito ,  Risho Koh ,  Jyonu Ri ,  Hisashi Takemura

发明人： Yukishige Saito ,  Risho Koh ,  Jyonu Ri ,  Hisashi Takemura

IPC分类号： H01L21/311

CPC分类号： H01L29/66757 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78636 ,  Y10S438/978

摘要： A method of manufacturing a semiconductor device of the present invention includes (a) sequentially forming a gate insulating film 14, a first conductive layer 15 and a first insulating film 16 on a semiconductor layer 13 provided on an insulating film 12; (b) selectively removing the semiconductor layer, the gate insulating film, the first conductive layer and the first insulating film to form a device isolation trench; (c) forming a second insulating film 17 in the device isolation [element separation] trench, wherein a height of an upper surface of the second insulating film is substantially coincident with that of an upper surface of the first insulating film; (d) removing a part of the second insulating film and the first insulating film such that a height of an upper surface of the exposed first conductive layer is substantially coincident with that of the top surface of the second insulating film; and (e) patterning the first conductive layer to form a gate electrode.

摘要翻译： 本发明的半导体器件的制造方法包括：（a）在设置在绝缘膜12上的半导体层13上依次形成栅极绝缘膜14，第一导电层15和第一绝缘膜16; （b）选择性地去除半导体层，栅极绝缘膜，第一导电层和第一绝缘膜，以形成器件隔离沟槽; （c）在器件隔离[元件分离]沟槽中形成第二绝缘膜17，其中第二绝缘膜的上表面的高度与第一绝缘膜的上表面的高度基本一致; （d）去除第二绝缘膜和第一绝缘膜的一部分，使得暴露的第一导电层的上表面的高度与第二绝缘膜的顶表面的高度基本一致; 和（e）图案化第一导电层以形成栅电极。

公开(公告)号：US07485923B2

公开(公告)日：2009-02-03

申请号：US10490599

申请日：2002-10-02

申请人： Hisashi Takemura ,  Risho Koh ,  Yukishige Saito ,  Jyonu Ri

发明人： Hisashi Takemura ,  Risho Koh ,  Yukishige Saito ,  Jyonu Ri

IPC分类号： H01L29/772

CPC分类号： H01L29/78696 ,  H01L21/26586 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621 ,  H01L2029/7863

摘要： A semiconductor device includes a first insulating layer, a semiconductor layer formed on the first insulating layer, a second insulating layer on a part of the semiconductor layer, and a gate electrode formed on the semiconductor layer through the second insulating layer. The semiconductor layer includes a low concentration region formed under the gate electrode through the second insulating layer, two high concentration regions which are formed in at least upper regions on outer sides of the low concentration region under the gate electrode through the second insulating layer, and have an impurity concentration higher than an impurity concentration of the low concentration region, respectively, and two source/drain regions which are formed in side portions of the high concentration regions to have low concentration region side end portions, respectively. A width of the high concentration region is equal to or less than 30 nm.

摘要翻译： 半导体器件包括第一绝缘层，形成在第一绝缘层上的半导体层，半导体层的一部分上的第二绝缘层和通过第二绝缘层形成在半导体层上的栅电极。 半导体层包括通过第二绝缘层形成在栅电极下方的低浓度区域，通过第二绝缘层形成在栅电极下方的低浓度区域的至少上侧区域中的至少上部区域的两个高浓度区域，以及 分别具有高于低浓度区域的杂质浓度的杂质浓度，以及分别形成在高浓度区域的侧部的两个源极/漏极区域，以分别具有低浓度区域侧端部。 高浓度区域的宽度等于或小于30nm。