公开(公告)号：US07505323B2

公开(公告)日：2009-03-17

申请号：US12025815

申请日：2008-02-05

Applicant: Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

Inventor： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

IPC: G11C11/34

CPC classification number: G11C16/10

Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Abstract translation: 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。

公开(公告)号：US20090043975A1

公开(公告)日：2009-02-12

申请号：US12246606

申请日：2008-10-07

Applicant: Benjamin Louie ,  Aaron Yip ,  Jin-Man Han

Inventor： Benjamin Louie ,  Aaron Yip ,  Jin-Man Han

IPC: G06F12/00

CPC classification number: G11C16/20 ,  G11C16/04 ,  G11C29/02 ,  G11C29/028

Abstract: Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit corresponding to a portion of the memory array. The reference trim circuit is adapted to store one or more reference control parameter values for respectively correcting one or more of the base control parameter values of the base trim circuitry for application to the portion of the memory array. The memory device may include an index circuit corresponding to the reference trim circuit. The index circuit is adapted to store one or more index parameter values for respectively selecting the one or more base control parameter values of the base trim circuitry for correction by the one or more reference control parameter values of the reference trim circuit.

Abstract translation: 提供了方法和装置。 存储器件具有存储器阵列，适用于存储存储器阵列共用的基本控制参数值的基本修剪电路以及与存储器阵列的一部分相对应的参考调整电路。 参考调整电路适于存储一个或多个参考控制参数值，用于分别校正基本调整电路的基本控制参数值中的一个或多个，以供应用于存储器阵列的该部分。 存储器件可以包括对应于参考调整电路的指数电路。 索引电路适于存储一个或多个索引参数值，用于分别选择基本修整电路的一个或多个基本控制参数值，以通过参考调整电路的一个或多个参考控制参数值进行校正。

公开(公告)号：US07447847B2

公开(公告)日：2008-11-04

申请号：US10894242

申请日：2004-07-19

Applicant: Benjamin Louie ,  Aaron Yip ,  Jin-Man Han

Inventor： Benjamin Louie ,  Aaron Yip ,  Jin-Man Han

IPC: G06F12/00

CPC classification number: G11C16/20 ,  G11C16/04 ,  G11C29/02 ,  G11C29/028

Abstract: Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit corresponding to a portion of the memory array. The reference trim circuit is adapted to store one or more reference control parameter values for respectively correcting one or more of the base control parameter values of the base trim circuitry for application to the portion of the memory array. The memory device may include an index circuit corresponding to the reference trim circuit. The index circuit is adapted to store one or more index parameter values for respectively selecting the one or more base control parameter values of the base trim circuitry for correction by the one or more reference control parameter values of the reference trim circuit.

Abstract translation: 提供了方法和装置。 存储器件具有存储器阵列，适用于存储存储器阵列共用的基本控制参数值的基本修剪电路以及与存储器阵列的一部分相对应的参考调整电路。 参考调整电路适于存储一个或多个参考控制参数值，用于分别校正基本调整电路的基本控制参数值中的一个或多个，以供应用于存储器阵列的该部分。 存储器件可以包括对应于参考调整电路的指数电路。 索引电路适于存储一个或多个索引参数值，用于分别选择基本修整电路的一个或多个基本控制参数值，以通过参考调整电路的一个或多个参考控制参数值进行校正。

公开(公告)号：US20080181032A1

公开(公告)日：2008-07-31

申请号：US11657951

申请日：2007-01-25

Applicant: Xiaojun Yu ,  Jin-man Han

Inventor： Xiaojun Yu ,  Jin-man Han

IPC: G11C7/00

CPC classification number: G11C11/5642 ,  G11C8/14 ,  G11C16/08 ,  G11C16/32

Abstract: Apparatus, systems, and methods described herein may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation may be delayed according to a delay period determined by a read level voltage magnitude associated with a plurality of memory cells included in the array.

Abstract translation: 本文描述的装置，系统和方法可以操作以在耦合到存储器阵列的控制电路处接收外部读取命令。 可以根据由包括在阵列中的多个存储器单元相关联的读取电平电压幅度确定的延迟周期来延迟单独的字线激活。

公开(公告)号：US20080130373A1

公开(公告)日：2008-06-05

申请号：US12025815

申请日：2008-02-05

Applicant: Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

Inventor： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

IPC: G11C16/04

CPC classification number: G11C16/10

Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Abstract translation: 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。

公开(公告)号：US20080097696A1

公开(公告)日：2008-04-24

申请号：US11873743

申请日：2007-10-17

Applicant: Mi Ryong Park ,  Tae Man Han ,  Man Seok Yang ,  Dong Sun Lim

Inventor： Mi Ryong Park ,  Tae Man Han ,  Man Seok Yang ,  Dong Sun Lim

IPC: G01C21/02

CPC classification number: G01C21/26 ,  G01S19/05 ,  H04L63/08

Abstract: Provided is a network global positioning system (GPS) terminal. The network GPS terminal includes: a GPS receiver receiving GPS data; a GPS processor processing the received GPS data to a predetermined form; a network communication part communicating with an external apparatus through a network in order to receive a request for the GPS data from the external apparatus, and transmit the processed GPS data to the external apparatus in response to the request; a security access controller authenticating the external apparatus; and a network management part managing connection information and security information of the external apparatus, the network communication part simultaneously communicating with at least one external apparatus using a TCP/IP protocol. A method of providing GPS data using a network is also provided.

Abstract translation: 提供了一种网络全球定位系统（GPS）终端。 网络GPS终端包括：GPS接收机接收GPS数据; GPS处理器将接收的GPS数据处理成预定的形式; 通过网络与外部设备通信的网络通信部件，以便从外部设备接收对GPS数据的请求，并且响应于该请求将处理的GPS数据发送到外部设备; 安全访问控制器认证外部设备; 以及管理外部设备的连接信息和安全信息的网络管理部分，所述网络通信部分使用TCP / IP协议与至少一个外部设备同时进行通信。 还提供了使用网络提供GPS数据的方法。

公开(公告)号：US07324394B1

公开(公告)日：2008-01-29

申请号：US11360181

申请日：2006-02-23

Applicant: Sei-Seung Yoon ,  Jin-Man Han ,  Seong-Ook Jung

Inventor： Sei-Seung Yoon ,  Jin-Man Han ,  Seong-Ook Jung

IPC: G11C7/00

CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/14

Abstract: A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.

Abstract translation: 本文公开了一种包括用于解析由存储器单元产生的数据信号的读出放大器的感测电路。 感测电路包括用于接收数据信号的位线，耦合到位线并被配置为对位线预充电的第一预充电器件，用于提供耦合到位线的偏置并被配置为提供 偏置到位线，以及被配置为至少一个预定电平的参考节点。 在一个实施例中，预定电平等于诸如地电位的低电位，而在另一实施例中等于诸如V DD的高电位。 一个或多个开关装置允许激活或去激活预充电装置，允许将位线预充电到特定电位，感测电路快速而准确地确定逻辑状态“1”或“0”是否为 应用于位线。

公开(公告)号：US20070081411A1

公开(公告)日：2007-04-12

申请号：US11635708

申请日：2006-12-07

Applicant: Jin-Man Han ,  Aaron Yip

Inventor： Jin-Man Han ,  Aaron Yip

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G06F12/0246 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/3427 ,  G11C29/76 ,  G11C29/82 ,  Y02D10/13

Abstract: A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.

Abstract translation: 非易失性存储器件具有将特定存储器块的页面重新分配给其他块，以便增加减少的干扰并增加可靠性。 包含来自期望的存储器块的重新分配的页面的每个重新分配块被耦合到字线驱动器。 这些字线驱动器具有全局字线的一部分作为输入。 期望的字线驱动器通过来自块解码器的适当选择信号和适当的全局字线上的指示来选择。 这将导致字线驱动程序在要重新分配的页面访问期望块时生成本地字线。

公开(公告)号：US07123521B1

公开(公告)日：2006-10-17

申请号：US11115489

申请日：2005-04-27

Applicant: Benjamin Louie ,  Yunqiu Wan ,  Aaron Yip ,  Jin-Man Han

Inventor： Benjamin Louie ,  Yunqiu Wan ,  Aaron Yip ,  Jin-Man Han

IPC: G11C7/10

CPC classification number: G11C7/1042 ,  G11C7/1051 ,  G11C16/26 ,  G11C2207/2245

Abstract: A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

Abstract translation: 描述了利用高速缓存读取操作模式的非易失性存储器，其中由读出放大器从存储器阵列读取/感测存储器的下一页，同时从存储器I / O缓冲器，其中下一页是用户选择的。 这种随机高速缓存读取模式允许具有随机页面读取功能的存储器，其中要读取的下一页数据的地址是用户可选择的，这受益于由于并发数据而导致的高速缓存读取操作模式的低等待时间 感测和数据I / O。

公开(公告)号：US20060171315A1

公开(公告)日：2006-08-03

申请号：US11223714

申请日：2005-09-08

Applicant: Da-Hye Choi ,  Hyun-Joo Kang ,  You-Hyeon Jeong ,  Tae-Man Han ,  Byeong-Sik Kim

Inventor： Da-Hye Choi ,  Hyun-Joo Kang ,  You-Hyeon Jeong ,  Tae-Man Han ,  Byeong-Sik Kim

IPC: H04L12/26

CPC classification number: H04L47/781 ,  H04L41/5003 ,  H04L41/5054 ,  H04L45/302 ,  H04L45/308 ,  H04L47/15 ,  H04L47/20 ,  H04L47/2408 ,  H04L47/70 ,  H04L47/783 ,  H04L47/808 ,  H04L47/829

Abstract: A resource allocation device includes a database of user and service information, a resource allocation management unit for determining whether a service request agrees with a service level agreement and whether it accepts a resource allocation request, a service level agreement unit for negotiating the service level agreement with the user, sending the received service request to the resource allocation management unit, acquiring the result of the resource allocation request, and transmitting the result of the resource allocation request to the user, a routing information management unit for obtaining a network configuring information, storing the network configuring information in the database, discovering the path to provide the service and storing the discovered path in the database to be reused and a policy control management unit for deciding a policy according to whether the service request and the resource allocation request are accepted.

Abstract translation: 资源分配装置包括用户和服务信息的数据库，用于确定服务请求是否符合服务级别协议以及是否接受资源分配请求的资源分配管理单元，用于协商服务级别协议的服务级别协议单元 向所述用户发送所接收的服务请求到所述资源分配管理单元，获取所述资源分配请求的结果，并向所述用户发送所述资源分配请求的结果;路由信息管理单元，用于获取网络配置信息; 将所述网络配置信息存储在所述数据库中，发现提供所述服务的路径并将所发现的路径存储在要重新使用的数据库中;以及策略控制管理单元，用于根据所述服务请求和所述资源分配请求是否被接受来决定策略 。