公开(公告)号：US06352900B1

公开(公告)日：2002-03-05

申请号：US09618404

申请日：2000-07-18

申请人： Manoj Mehrotra ,  Jerry Che-Jen Hu ,  Amitava Chatterjee ,  Mark S. Rodder

发明人： Manoj Mehrotra ,  Jerry Che-Jen Hu ,  Amitava Chatterjee ,  Mark S. Rodder

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/28247

摘要： A method for controlled oxide growth on transistor gates. A first film (40) is formed on a semiconductor substrate (10). The film is implanted with a first species and patterned to form a transistor gate (45) . The transistor gate (45) and the semiconductor substrate (10) is implanted with a second species and the transistor gate (45) oxidized to produce an oxide film (80) on the side surface of the transistor gate (45).

摘要翻译： 一种在晶体管栅极上控制氧化物生长的方法。 第一膜（40）形成在半导体衬底（10）上。 该膜植入第一种并图案化以形成晶体管栅极（45）。 晶体管栅极（45）和半导体衬底（10）被注入第二种类，并且晶体管栅极（45）被氧化以在晶体管栅极（45）的侧表面上产生氧化物膜（80）。

公开(公告)号：US06228725B1

公开(公告)日：2001-05-08

申请号：US09281543

申请日：1999-03-30

申请人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Mark S. Rodder ,  Ih-Chin Chen

发明人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Mark S. Rodder ,  Ih-Chin Chen

IPC分类号： H01L21336

CPC分类号： H01L29/66575 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/7838

摘要： A low power transistor (70, 70′) formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80′) of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82′, 84′) of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80′).

摘要翻译： 形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。 晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。 通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。 第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

公开(公告)号：US06093610A

公开(公告)日：2000-07-25

申请号：US94978

申请日：1998-06-16

申请人： Mark S. Rodder

发明人： Mark S. Rodder

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/10 ,  H01L29/49

CPC分类号： H01L29/66492 ,  H01L29/1083 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/6659 ,  H01L21/2254 ,  H01L21/2255 ,  H01L29/66545

摘要： A self-aligned pocket process for formation of CMOS devices and the devices by means of a sidewall doped overlayer to achieve deep sub-0.1 .mu.m CMOS with reduced gate length variation. The localized pocket results in reduced C.sub.J. The method includes providing a semiconductor substrate and forming a gate electrode over the substrate separated from the substrate by an electrical insulator. A preferably electrically insulating sidewall material which contains a dopant of predetermined conductivity type is formed over and either in contact with or spaced from the sidewalls of the gate electrode. The dopant is caused to migrate into the substrate beneath the sidewall material with some lateral movement to form a pocket of the predetermined conductivity type in the substrate. A further sidewall can be added to the sidewall material after pocket formation. The sidewall material can be later removed. Drain extensions and/or source/drain regions are formed in the substrate of conductivity type opposite the predetermined conductivity type, with or without use of sidewalls as a mask to provide minimal overlap between the drain extensions and/or source/drain regions and the pocket.

摘要翻译： 用于通过侧壁掺杂覆盖层形成CMOS器件和器件的自对准口袋工艺，以实现具有减小的栅极长度变化的深度低于0.1μm的CMOS。 本地口袋导致CJ减少。 该方法包括提供半导体衬底，并在通过电绝缘体从衬底分离的衬底上形成栅电极。 包含预定导电类型的掺杂剂的优选电绝缘侧壁材料形成在栅电极的侧壁上并与栅电极的侧壁接触或间隔开。 导致掺杂剂在侧壁材料的下方迁移到衬底中，并具有一些横向运动，以在衬底中形成预定导电类型的凹穴。 袋形成后可以在侧壁材料上添加另外的侧壁。 侧壁材料可以稍后去除。 在具有或不使用侧壁作为掩模的情况下，在与预定导电类型相反的导电类型的衬底中形成漏极延伸部和/或源极/漏极区域，以在漏极延伸部分和/或源极/漏极区域和凹部之间提供最小重叠 。

公开(公告)号：US5918145A

公开(公告)日：1999-06-29

申请号：US481900

申请日：1995-06-07

申请人： Mark S. Rodder

发明人： Mark S. Rodder

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L211/3205 ,  H01L21/324

CPC分类号： H01L23/53257 ,  H01L21/76886 ,  H01L23/485 ,  H01L2924/0002

摘要： A microelectronic device (10) provides decreased use of bar area to form contacts between a conductive strap (24) or interconnect and subsequent levels. The conductive strap comprises a conducting layer (130) and an overlying semiconducting layer (132). Connection to subsequent levels is made generally overlying substrate conductive areas such as a gate (14) and/or a moat (16). Connection to conductive sublayer (130) is accomplished by doping an overlying semiconductor sublayer (132). Any counter-doping of substrate conductive areas is blocked by an overlying well of dopant-masking (33) or sufficiently thick semiconducting (32) material.

摘要翻译： 微电子器件（10）提供减少的条形面积的使用以在导电带（24）或互连和随后的级之间形成接触。 导电带包括导电层（130）和上覆半导体层（132）。 通常覆盖衬底导电区域（例如门（14）和/或护城河（16））与后续层的连接。 通过掺杂上覆的半导体子层（132）来实现与导电子层（130）的连接。 衬底导电区域的任何反掺杂被掺杂剂掩蔽（33）或足够厚的半导体（32）材料的上覆阱阻挡。

公开(公告)号：US5264385A

公开(公告)日：1993-11-23

申请号：US805393

申请日：1991-12-09

申请人： Mark S. Rodder

发明人： Mark S. Rodder

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11

摘要： A novel layout performing SRAM cells is disclosed wherein conductive straps (36) connect first and second driver gates (22, 24) to second and first drains (33, 31) respectively without connecting the moat of one cell with the moat of another cell such that the conductive straps are never in a DC current path.

公开(公告)号：US5223736A

公开(公告)日：1993-06-29

申请号：US704232

申请日：1991-05-22

申请人： Mark S. Rodder

发明人： Mark S. Rodder

IPC分类号： H01L21/763

CPC分类号： H01L21/763

摘要： A structure for and method of forming a trench in a semiconductor body is disclosed herein. A field oxide 16 is grown over a portion of n-well 8 where trench 26 is to be formed. Nitride layer 20 and TEOS oxide layer 22 are deposited. Resist 24 is patterned and TEOS layer 22, nitride layer 20, and field oxide layer 16 are etched. Resist 24 is removed and trench 26 is etched through n-well 8 and into substrate 4. Thin oxide 28 is then grown on the sidewalls of trench 26. Polysilicon is deposited into trench 26 and etched back to form polysilicon plug 30. Sidewall oxide 32, to prevent voids in the topography of trench 26, is formed on top of polysilicon plug 30 along the outer edges of trench 26. To prevent leakage into trench 26, a thick thermal oxide cap 34 is grown over trench 26.

摘要翻译： 本文公开了一种在半导体本体中形成沟槽的结构和方法。 在要形成沟槽26的n阱8的一部分上生长场氧化物16。 氮化物层20和TEOS氧化物层22沉积。 抗蚀剂24被图案化，TEOS层22，氮化物层20和场氧化物层16被蚀刻。 去除抗蚀剂24，并且通过n阱8蚀刻沟槽26并进入衬底4.然后在沟槽26的侧壁上生长薄氧化物28.多晶硅沉积到沟槽26中并被回蚀以形成多晶硅插塞30.侧壁氧化物32 ，以防止沟槽26的形状中的空隙沿着沟槽26的外边缘形成在多晶硅插塞30的顶部上。为了防止泄漏到沟槽26中，厚的热氧化物盖34生长在沟槽26上。

公开(公告)号：US5145799A

公开(公告)日：1992-09-08

申请号：US647579

申请日：1991-01-30

申请人： Mark S. Rodder

发明人： Mark S. Rodder

IPC分类号： H01L21/02 ,  H01L21/8244

CPC分类号： H01L28/40 ,  H01L27/11

摘要： This is an SRAM cell and the cell can comprise: two NMOS drive transistors; two PMOS load transistors; first and second bottom capacitor plates 50, 52, with the first plate 50 being over a gate 34 of one of the drive transistors and the second plate 52 being over a gate 40 of another of the drive transistors; a layer of dielectric material 68 over the first and second bottom capacitor plates; and first and second top capacitor plates 20, 26 over the dielectric layer, with the first top capacitor 20 plate forming a gate of one of the load transistors and with the second top capacitor plate 26 forming a gate of another of the load transistors, whereby the capacitor plates form two cross-coupled capacitors between the gates of the drive transistors and the stability of the cell is enhanced. This is also a method of forming an SRAM cell.

摘要翻译： 这是一个SRAM单元，单元可以包括：两个NMOS驱动晶体管; 两个PMOS负载晶体管; 第一和第二底部电容器板50,52，其中第一板50位于驱动晶体管之一的栅极34上，而第二板52位于另一个驱动晶体管的栅极40之上; 在第一和第二底部电容器板上的电介质材料层68; 以及在电介质层上的第一和第二顶部电容器板20,26，其中第一顶部电容器20板形成负载晶体管中的一个的栅极，并且与第二顶部电容器板26形成另一个负载晶体管的栅极，由此 电容器板在驱动晶体管的栅极之间形成两个交叉耦合的电容器，并且增强了电池的稳定性。 这也是形成SRAM单元的方法。

公开(公告)号：US5079180A

公开(公告)日：1992-01-07

申请号：US568305

申请日：1990-08-16

申请人： Mark S. Rodder ,  Richard A. Chapman

发明人： Mark S. Rodder ,  Richard A. Chapman

IPC分类号： H01L21/336 ,  H01L29/08

CPC分类号： H01L29/66628 ,  H01L29/0847

摘要： A raised source/drain transistor is provided having thin sidewall spacing insulators (54) adjacent the transistor gate (48). A first sidewall spacer (64) is disposed adjacent thin sidewall spacing insulator (54) and raised source/drain region (60). A second sidewall spacer (66) is formed at the interface between field insulating region (44) and raised source/drain region (60).

摘要翻译： 提供了一个升高的源极/漏极晶体管，其具有与晶体管栅极（48）相邻的薄的侧壁间隔绝缘体（54）。 第一侧壁间隔物（64）邻近薄侧壁间隔绝缘体（54）和升高的源/漏区（60）设置。 第二侧壁间隔物（66）形成在场绝缘区域（44）和凸起源极/漏极区域（60）之间的界面处。

公开(公告)号：US4999690A

公开(公告)日：1991-03-12

申请号：US452855

申请日：1989-12-19

申请人： Mark S. Rodder

发明人： Mark S. Rodder

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/786

CPC分类号： H01L29/78618 ,  H01L29/41733

摘要： A thin film field effect transistor and method for forming the same are disclosed. Conductive moat bodies 16 and 18 are formed on a surface 12 of an insulator substrate 10. A semiconductor channel layer 20 is formed covering the moat bodies 16 and 18 and the surface 12. A gate insulator layer 22 is formed covering the channel layer 20 between the moat bodies 16 and 18. A gate conductor 26 is formed outwardly from the gate insulator layer 22. Moat bodies 16 and 18 provide efficient contact points for a source contact 56 and a drain contact 60. Additionally, moat bodies 16 and 18 provide additional material from which silicide bodies 48 and 52 may be optionally formed.

摘要翻译： 公开了薄膜场效应晶体管及其形成方法。 导电沟槽体16和18形成在绝缘体基板10的表面12上。形成覆盖沟槽体16,18和表面12的半导体沟道层20.形成栅极绝缘体层22，覆盖沟道层20之间 护城河主体16和18.门导体26从栅极绝缘体层22向外形成。护城河体16和18为源接触56和排水接触60提供有效的接触点。另外，护城河体16和18提供额外的 可以任选地形成硅化物体48和52的材料。

公开(公告)号：US20160111421A1

公开(公告)日：2016-04-21

申请号：US14828509

申请日：2015-08-17

申请人： Mark S. RODDER ,  Rwik SENGUPTA ,  Borna OBRADOVIC

发明人： Mark S. RODDER ,  Rwik SENGUPTA ,  Borna OBRADOVIC

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L27/0886 ,  H01L21/28123 ,  H01L21/823437 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： An integrated circuit comprises at least one block comprising a first cell and a second cell. The first cell comprises a first FET formed with a first contacted poly pitch (CPP), and the second cell comprises a second FET formed with a second CPP. The first CPP is greater than the second CPP. The first FET is part of a critical-speed path, and the second FET is part of a noncritical-speed path, in which the critical-speed path operates at a faster speed than the noncritical-speed path. The first FET and the second FET each comprise a planar FET, a finFET, a gate-all-around FET or a nanosheet FET. A method for forming the integrated circuit is also disclosed.

摘要翻译： 集成电路包括至少一个包括第一单元和第二单元的块。 第一单元包括形成有第一接触聚间距（CPP）的第一FET，并且第二单元包括由第二CPP形成的第二FET。 第一个CPP大于第二个CPP。 第一个FET是临界速度路径的一部分，第二个FET是非临界速度路径的一部分，其中临界速度路径以比非临界速度路径更快的速度运行。 第一FET和第二FET各自包括平面FET，finFET，栅极全环FET或纳米片FET。 还公开了一种用于形成集成电路的方法。