公开(公告)号：US10283638B2

公开(公告)日：2019-05-07

申请号：US15086015

申请日：2016-03-30

Applicant: Jorge A. Kittl ,  Ganesh Hegde ,  Robert C. Bowen ,  Mark S. Rodder

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack comprises a plurality of sacrificial layers in which each sacrificial layer comprises a first lattice parameter; and at least one channel layer comprising a second lattice parameter that is different from the first lattice parameter and in which each channel layer is disposed between and in contact with two sacrificial layers. The stack is formed on an underlayer in which a sacrificial layer is in contact with the underlayer. The underlayer comprises a third lattice parameter that substantially matches the lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were was allow to relax coherently.

公开(公告)号：US20150243756A1

公开(公告)日：2015-08-27

申请号：US14698402

申请日：2015-04-28

Applicant: Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

Inventor： Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L29/66

CPC classification number: H01L29/66522 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include InyGa1−yAs, and y is in a range of about 0.3 to about 0.5.

Abstract translation: 提供了形成finFET的方法。 所述方法可以包括在衬底上形成包括铟（In）的鳍状沟道区域，形成与衬底上的沟道区相邻的深源极/漏极区域，并在沟道区域和深度之间形成源极/漏极延伸区域 源/漏区。 源极/漏极延伸区域的相对侧壁可以分别接触沟道区域和深源极/漏极区域，并且源极/漏极延伸区域可以包括In y Ga 1-y As，y在约0.3至约0.5的范围内。

公开(公告)号：US09064699B2

公开(公告)日：2015-06-23

申请号：US14258704

申请日：2014-04-22

Applicant: Wei-E Wang ,  Mark S. Rodder ,  Robert C. Bowen

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Robert C. Bowen

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/02488 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/66795

Abstract: Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods are provided. The methods may include forming an oxide layer on a substrate and forming a recess in the oxide layer and the substrate. The methods may further include forming an epitaxially grown semiconductor pattern in the recess that contacts a sidewall of the substrate at an interface between the oxide layer and the substrate and defines an upper surface of a void in the recess in the substrate.

Abstract translation: 提供了形成包括减少的位错缺陷的半导体图案的方法和使用这些方法形成的器件。 所述方法可以包括在衬底上形成氧化物层并在氧化物层和衬底中形成凹陷。 所述方法还可以包括在所述凹部中形成外延生长的半导体图案，所述外延生长的半导体图案在所述氧化物层和所述衬底之间的界面处接触所述衬底的侧壁，并且限定所述衬底的所述凹部中的空隙的上表面。

公开(公告)号：USD571642S1

公开(公告)日：2008-06-24

申请号：US29259967

申请日：2006-05-18

Applicant: Mark S. Rodder

Designer： Mark S. Rodder

公开(公告)号：US07371658B2

公开(公告)日：2008-05-13

申请号：US10870020

申请日：2004-06-17

Applicant: Rick L. Wise ,  Mark S. Rodder

Inventor： Rick L. Wise ,  Mark S. Rodder

IPC: H01L21/76 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/76224 ,  H01L21/823807 ,  H01L21/823878

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having a buffer layer (133) located on sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

Abstract translation: 本发明提供一种沟槽隔离结构及其制造方法以及包括该沟槽隔离结构的集成电路的制造方法。 在一个实施例中，沟槽隔离结构（130）包括位于衬底（110）内的沟槽，沟槽具有位于其侧壁上的缓冲层（133）。 沟槽隔离结构（130）还包括位于缓冲层（133）上的阻挡层（135）和位于阻挡层（135）上方并且基本上填充沟槽的填充材料（138）。

公开(公告)号：US06352900B1

公开(公告)日：2002-03-05

申请号：US09618404

申请日：2000-07-18

Applicant: Manoj Mehrotra ,  Jerry Che-Jen Hu ,  Amitava Chatterjee ,  Mark S. Rodder

Inventor： Manoj Mehrotra ,  Jerry Che-Jen Hu ,  Amitava Chatterjee ,  Mark S. Rodder

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/28247

Abstract: A method for controlled oxide growth on transistor gates. A first film (40) is formed on a semiconductor substrate (10). The film is implanted with a first species and patterned to form a transistor gate (45) . The transistor gate (45) and the semiconductor substrate (10) is implanted with a second species and the transistor gate (45) oxidized to produce an oxide film (80) on the side surface of the transistor gate (45).

Abstract translation: 一种在晶体管栅极上控制氧化物生长的方法。 第一膜（40）形成在半导体衬底（10）上。 该膜植入第一种并图案化以形成晶体管栅极（45）。 晶体管栅极（45）和半导体衬底（10）被注入第二种类，并且晶体管栅极（45）被氧化以在晶体管栅极（45）的侧表面上产生氧化物膜（80）。

公开(公告)号：US06228725B1

公开(公告)日：2001-05-08

申请号：US09281543

申请日：1999-03-30

Applicant: Mahalingam Nandakumar ,  Amitava Chatterjee ,  Mark S. Rodder ,  Ih-Chin Chen

Inventor： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Mark S. Rodder ,  Ih-Chin Chen

IPC: H01L21336

CPC classification number: H01L29/66575 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/7838

Abstract: A low power transistor (70, 70′) formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80′) of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82′, 84′) of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80′).

Abstract translation: 形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。 晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。 通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。 第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

公开(公告)号：US06093610A

公开(公告)日：2000-07-25

申请号：US94978

申请日：1998-06-16

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/10 ,  H01L29/49

CPC classification number: H01L29/66492 ,  H01L29/1083 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/6659 ,  H01L21/2254 ,  H01L21/2255 ,  H01L29/66545

Abstract: A self-aligned pocket process for formation of CMOS devices and the devices by means of a sidewall doped overlayer to achieve deep sub-0.1 .mu.m CMOS with reduced gate length variation. The localized pocket results in reduced C.sub.J. The method includes providing a semiconductor substrate and forming a gate electrode over the substrate separated from the substrate by an electrical insulator. A preferably electrically insulating sidewall material which contains a dopant of predetermined conductivity type is formed over and either in contact with or spaced from the sidewalls of the gate electrode. The dopant is caused to migrate into the substrate beneath the sidewall material with some lateral movement to form a pocket of the predetermined conductivity type in the substrate. A further sidewall can be added to the sidewall material after pocket formation. The sidewall material can be later removed. Drain extensions and/or source/drain regions are formed in the substrate of conductivity type opposite the predetermined conductivity type, with or without use of sidewalls as a mask to provide minimal overlap between the drain extensions and/or source/drain regions and the pocket.

Abstract translation: 用于通过侧壁掺杂覆盖层形成CMOS器件和器件的自对准口袋工艺，以实现具有减小的栅极长度变化的深度低于0.1μm的CMOS。 本地口袋导致CJ减少。 该方法包括提供半导体衬底，并在通过电绝缘体从衬底分离的衬底上形成栅电极。 包含预定导电类型的掺杂剂的优选电绝缘侧壁材料形成在栅电极的侧壁上并与栅电极的侧壁接触或间隔开。 导致掺杂剂在侧壁材料的下方迁移到衬底中，并具有一些横向运动，以在衬底中形成预定导电类型的凹穴。 袋形成后可以在侧壁材料上添加另外的侧壁。 侧壁材料可以稍后去除。 在具有或不使用侧壁作为掩模的情况下，在与预定导电类型相反的导电类型的衬底中形成漏极延伸部和/或源极/漏极区域，以在漏极延伸部分和/或源极/漏极区域和凹部之间提供最小重叠 。

公开(公告)号：US5918145A

公开(公告)日：1999-06-29

申请号：US481900

申请日：1995-06-07

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L211/3205 ,  H01L21/324

CPC classification number: H01L23/53257 ,  H01L21/76886 ,  H01L23/485 ,  H01L2924/0002

Abstract: A microelectronic device (10) provides decreased use of bar area to form contacts between a conductive strap (24) or interconnect and subsequent levels. The conductive strap comprises a conducting layer (130) and an overlying semiconducting layer (132). Connection to subsequent levels is made generally overlying substrate conductive areas such as a gate (14) and/or a moat (16). Connection to conductive sublayer (130) is accomplished by doping an overlying semiconductor sublayer (132). Any counter-doping of substrate conductive areas is blocked by an overlying well of dopant-masking (33) or sufficiently thick semiconducting (32) material.

Abstract translation: 微电子器件（10）提供减少的条形面积的使用以在导电带（24）或互连和随后的级之间形成接触。 导电带包括导电层（130）和上覆半导体层（132）。 通常覆盖衬底导电区域（例如门（14）和/或护城河（16））与后续层的连接。 通过掺杂上覆的半导体子层（132）来实现与导电子层（130）的连接。 衬底导电区域的任何反掺杂被掺杂剂掩蔽（33）或足够厚的半导体（32）材料的上覆阱阻挡。

公开(公告)号：US5264385A

公开(公告)日：1993-11-23

申请号：US805393

申请日：1991-12-09

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L27/11

Abstract: A novel layout performing SRAM cells is disclosed wherein conductive straps (36) connect first and second driver gates (22, 24) to second and first drains (33, 31) respectively without connecting the moat of one cell with the moat of another cell such that the conductive straps are never in a DC current path.