公开(公告)号：US09917158B2

公开(公告)日：2018-03-13

申请号：US14942193

申请日：2015-11-16

申请人： Jorge A. Kittl ,  Borna Josip Obradovic ,  Robert Christopher Bowen ,  Mark S. Rodder

发明人： Jorge A. Kittl ,  Borna Josip Obradovic ,  Robert Christopher Bowen ,  Mark S. Rodder

IPC分类号： H01L29/66 ,  H01L29/267 ,  H01L29/78 ,  H01L21/285 ,  H01L29/45 ,  H01L29/08

CPC分类号： H01L29/267 ,  H01L21/28575 ,  H01L29/0847 ,  H01L29/452 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device can include a channel region with a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device and a metal contact. A source/drain region can include a semiconductor material alloy including a second semiconductor material and at least one heterojunction located between the metal contact and the channel region, wherein the heterojunction forms a band-edge offset for the majority carrier that is less than or equal to about 0.2 eV.

公开(公告)号：US20160163796A1

公开(公告)日：2016-06-09

申请号：US14952152

申请日：2015-11-25

申请人： Borna J. Obradovic ,  Ryan Hatcher ,  Robert C. Bowen ,  Mark S. Rodder

发明人： Borna J. Obradovic ,  Ryan Hatcher ,  Robert C. Bowen ,  Mark S. Rodder

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/16

CPC分类号： H01L29/0676 ,  B82B3/0014 ,  B82Y10/00 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/16 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

摘要： A device may include a nanosheet field effect transistor (FET) that may include a substrate, a well that is doped with impurities at a surface of the substrate, a channel including a plurality of stacked nanosheets, a gate, a conductive material, and an isolation layer. Ones of the plurality of stacked nanosheets may include a semiconductor material that may be doped with impurities of the same conductivity type as the impurities of the well. The conductive material may be adjacent the plurality of nanosheets and may electrically connect ones of the plurality of nanosheets to the well. The isolation layer may electrically insulate the well from the workfunction metal.

摘要翻译： 器件可以包括纳米片状场效应晶体管（FET），其可以包括衬底，在衬底的表面上掺杂有杂质的阱，包括多个堆叠的纳米片，沟道，导电材料和 隔离层 多个堆叠的纳米片的一部分可以包括半导体材料，其可掺杂与阱的杂质相同的导电类型的杂质。 导电材料可以与多个纳米片相邻，并且可以将多个纳米片中的一个纳米片电连接到该孔。 隔离层可以将孔与功函数金属电绝缘。

公开(公告)号：US20150145003A1

公开(公告)日：2015-05-28

申请号：US14534453

申请日：2014-11-06

申请人： Mark S. Rodder ,  Borna J. Obradovic ,  Robert C. Bowen

发明人： Mark S. Rodder ,  Borna J. Obradovic ,  Robert C. Bowen

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L29/66 ,  H01L29/165

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7848

摘要： FinFET semiconductor devices and methods of forming the same are provided. The finFET semiconductor devices may include an insulator layer, a bottom semiconductor layer on the insulator layer, a channel fin on the bottom semiconductor layer, a source region on the bottom semiconductor layer and adjacent a first side of the channel fin, and a drain region on the bottom semiconductor layer and adjacent a second side of the channel fin opposite the first side.

摘要翻译： 提供FinFET半导体器件及其形成方法。 finFET半导体器件可以包括绝缘体层，绝缘体层上的底部半导体层，底部半导体层上的沟道鳍片，底部半导体层上的源极区域和与沟道鳍片的第一侧相邻的源区域，以及漏极区域 在底部半导体层上并且与第一侧相对的沟槽的第二侧相邻。

公开(公告)号：US07459734B2

公开(公告)日：2008-12-02

申请号：US10846741

申请日：2004-05-14

申请人： Keith A. Joyner ,  Mark S. Rodder

发明人： Keith A. Joyner ,  Mark S. Rodder

IPC分类号： H01L31/062 ,  H01L31/113

CPC分类号： H01L21/76897 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed on the first surface, a gate electrode disposed on the dielectric layer, an insulation layer adjacent at least part of the gate electrode, and a nitride spacer layer adjacent at least part of the insulation layer. The method also includes depositing, on part of the first surface, a material that will react with the semiconductor layer to form silicide and removing the unreacted material. The method further includes etching the nitride spacer layer, depositing a pre-metal spacer layer adjacent at least part of the nitride spacer layer and at least part of the first surface, etch removing a portion of the pre-metal spacer layer to expose part of the silicided portion of the first surface, and forming a contact with the silicided portion of the first surface.

摘要翻译： 一种制造晶体管的方法，包括：提供具有第一表面的半导体层，设置在第一表面上的电介质层，设置在电介质层上的栅电极，与栅电极的至少一部分相邻的绝缘层的晶体管组件， 以及邻近绝缘层的至少一部分的氮化物间隔层。 该方法还包括在第一表面的一部分上沉积将与半导体层反应以形成硅化物并除去未反应材料的材料。 该方法还包括蚀刻氮化物间隔层，沉积与氮化物间隔层的至少一部分相邻的预金属间隔层和至少部分第一表面，蚀刻去除前金属间隔层的一部分以暴露部分 第一表面的硅化部分，并与第一表面的硅化部分形成接触。

公开(公告)号：US07160782B2

公开(公告)日：2007-01-09

申请号：US10870016

申请日：2004-06-17

申请人： Rick L. Wise ,  Mark S. Rodder

发明人： Rick L. Wise ,  Mark S. Rodder

IPC分类号： H01L21/762

CPC分类号： H01L21/823878 ,  H01L21/76237 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having an implanted buffer layer (133) located in the sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the implanted buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

摘要翻译： 本发明提供一种沟槽隔离结构及其制造方法以及包括该沟槽隔离结构的集成电路的制造方法。 在一个实施例中，沟槽隔离结构（130）包括位于衬底（110）内的沟槽，沟槽具有位于其侧壁中的注入缓冲层（133）。 沟槽隔离结构（130）还包括位于注入缓冲层（133）上的阻挡层（135）和位于阻挡层（135）上方并且基本上填充沟槽的填充材料（138）。

公开(公告)号：US06686300B2

公开(公告)日：2004-02-03

申请号：US10055262

申请日：2001-10-25

申请人： Manoj Mehrotra ,  John N. Randall ,  Mark S. Rodder

发明人： Manoj Mehrotra ,  John N. Randall ,  Mark S. Rodder

IPC分类号： H01L21302

CPC分类号： H01L29/4238 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/1033 ,  Y10S438/945

摘要： A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.

公开(公告)号：US06660595B2

公开(公告)日：2003-12-09

申请号：US09839718

申请日：2001-04-20

申请人： Mark S. Rodder

发明人： Mark S. Rodder

IPC分类号： H01L218236

CPC分类号： H01L21/26586 ,  H01L21/823418 ,  Y10S438/982

摘要： A method of fabricating different transistor structures with the same mask. A masking layer (214) has two openings (204, 202) that expose two transistor areas (304,302). The width of the second opening (202) is adjusted such that the angled implant is substantially blocked from the second transistor area (302). The angled implant forms pocket regions in the first transistor area (304). The same masking layer (214) may then be used to implant source and drain extension regions in both the first and second transistor areas (304, 302).

摘要翻译： 制造具有相同掩模的不同晶体管结构的方法。 掩模层（214）具有暴露两个晶体管区域（304,302）的两个开口（204,202）。 调节第二开口（202）的宽度，使得成角度的植入物基本上被阻挡于第二晶体管区域（302）。 成角度的植入物在第一晶体管区域（304）中形成袋区域。 然后可以使用相同的掩模层（214）来在第一和第二晶体管区域（304,302）中注入源极和漏极延伸区域。

公开(公告)号：US06413824B1

公开(公告)日：2002-07-02

申请号：US09589953

申请日：2000-06-08

申请人： Amitava Chatterjee ,  Alec J. Morton ,  Mark S. Rodder ,  Taylor R. Efland ,  Chin-Yu Tsai ,  James R. Hellums

发明人： Amitava Chatterjee ,  Alec J. Morton ,  Mark S. Rodder ,  Taylor R. Efland ,  Chin-Yu Tsai ,  James R. Hellums

IPC分类号： H01L218234

CPC分类号： H01L21/823814 ,  H01L21/823807

摘要： High performance digital transistors (140) and analog transistors (144) are formed at the same time. The digital transistors (140) include pocket regions (134) for optimum performance. These pocket regions (134) are partially or completely suppressed from at least the drain side of the analog transistors (144) to provide a flat channel doping profile on the drain side. The flat channel doping profile provides high early voltage and higher gain. The suppression is accomplished by using the HVLDD implants for the analog transistors (144).

摘要翻译： 高性能数字晶体管（140）和模拟晶体管（144）同时形成。 数字晶体管（140）包括用于最佳性能的口袋区域（134）。 这些袋区域（134）从模拟晶体管（144）的至少漏极侧部分地或完全被抑制，以在漏极侧提供平坦的沟道掺杂分布。 平坦沟道掺杂分布提供高的早期电压和更高的增益。 通过使用用于模拟晶体管（144）的HVLDD种植体实现抑制。

公开(公告)号：US06246091B1

公开(公告)日：2001-06-12

申请号：US09335242

申请日：1999-06-17

申请人： Mark S. Rodder

发明人： Mark S. Rodder

IPC分类号： H01L2976

CPC分类号： H01L29/0847 ,  H01L21/28114 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66628

摘要： A lateral MOSFET (100) and a method for making the same. A two layer raised source/drain region (106) is located adjacent a gate structure (112). The first layer (106a) of the raised source drain is initially doped p-type and the second layer (106b) of the raised source/drain region is doped n-type. P-type dopants from first layer (106a) are diffused into the substrate to form a pocket barrier region (105). N-type dopants from second layer (106b) diffuse into first layer (106a) so that it becomes n-type and into the substrate to form source/drain junction regions (104). P-type pocket barrier region (105) thus provides a barrier between the source/drain junction regions (104) and the channel region (108).

摘要翻译： 横向MOSFET（100）及其制造方法。 两层隆起的源极/漏极区（106）位于栅极结构（112）附近。 凸起的源极漏极的第一层（106a）最初是掺杂p型的，凸起的源极/漏极区的第二层（106b）被掺杂为n型。 来自第一层（106a）的P型掺杂剂扩散到衬底中以形成袋状阻挡区（105）。 来自第二层（106b）的N型掺杂剂扩散到第一层（106a）中，使得其变为n型并进入衬底以形成源极/漏极结区（104）。 因此，P型袋状阻挡区域（105）在源极/漏极结区域（104）和沟道区域（108）之间提供阻挡层。

公开(公告)号：US6083836A

公开(公告)日：2000-07-04

申请号：US216127

申请日：1998-12-18

申请人： Mark S. Rodder

发明人： Mark S. Rodder

IPC分类号： H01L29/786 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/00

CPC分类号： H01L29/66628 ,  H01L21/28079 ,  H01L21/82345 ,  H01L29/41783

摘要： Transistors may be fabricated by isolating a first region (16) of a semiconductor layer from a second region (18) of the semiconductor layer (12). A first disposable gate structure (26) of the first transistor may be formed over the first region (16) of the semiconductor layer (12). The first disposable gate structure (26) may comprise a replaceable material. A second disposable gate structure (28) of the second complementary transistor may be formed over the second region (18) of the semiconductor layer (12). A replacement layer (70) may be formed over the first disposable gate structure (26). The replacement layer (70) may comprise a replacement material. At least a portion of the replaceable material of the first disposable gate structure (26) may be substitutionally replaced with the replacement material of the replacement layer (70) to form a first gate structure (80).

摘要翻译： 可以通过将半导体层的第一区域（16）与半导体层（12）的第二区域（18）隔离来制造晶体管。 第一晶体管的第一一次性栅极结构（26）可以形成在半导体层（12）的第一区域（16）上。 第一一次性门结构（26）可以包括可更换的材料。 第二互补晶体管的第二一次性栅极结构（28）可以形成在半导体层（12）的第二区域（18）上。 替换层（70）可以形成在第一一次性栅极结构（26）上。 替换层（70）可以包括替换材料。 第一一次性栅极结构（26）的可更换材料的至少一部分可以用替代层（70）的替换材料替代地形成第一栅极结构（80）。