公开(公告)号：US20250147840A1

公开(公告)日：2025-05-08

申请号：US18930772

申请日：2024-10-29

Applicant: Micron Technology, Inc.

Inventor： Casto Salobrena Garcia ,  Kevin Gajera

IPC: G06F11/10

Abstract: Methods, systems, and devices for implicit storage of metadata at a memory device are described. A memory device may perform an error correction code (ECC) decoding operation on a first set of parity bits for a set of data and a second set of parity bits for the set of data. The memory device may compare the first set of parity bits to the second set of parity bits based on the ECC decoding operation indicating that the set of data has an uncorrectable error, the first set of parity bits to the second set of parity bits. The memory device may recover metadata information, for the set of data, previously received by the memory device, based on the comparison.

公开(公告)号：US20250147831A1

公开(公告)日：2025-05-08

申请号：US18935129

申请日：2024-11-01

Applicant: Micron Technology, Inc.

Inventor： Fanqi Wu ,  Zhenlei Shen ,  Jiangli Zhu ,  Tingjun Xie

IPC: G06F11/07

Abstract: A processing device in a memory sub-system identifies a read error associated with a block and determines a charge loss value associated with the block. The processing device determines whether the charge loss value is greater than or equal to a charge loss threshold. Responsive to determining the charge loss value is greater than or equal to the charge loss threshold, the block is identified as a healthy block.

公开(公告)号：US20250147695A1

公开(公告)日：2025-05-08

申请号：US18955746

申请日：2024-11-21

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Jonathan S. Parry ,  Nitul Gohain

IPC: G06F3/06 ,  G06F12/02

Abstract: Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.

公开(公告)号：US20250147679A1

公开(公告)日：2025-05-08

申请号：US18947633

申请日：2024-11-14

Applicant: Micron Technology, Inc.

Inventor： Liang Ge

IPC: G06F3/06 ,  G06F1/324

Abstract: Methods, systems, and devices for a light hibernation mode for memory are described. A memory system may include volatile memory and non-volatile memory and may be configured to operate according to a first mode of operation (e.g., associated with relatively high power consumption), a light hibernation mode (e.g., a second mode associated with decreased power consumption in comparison to the first mode), and a full hibernation mode (e.g., a third mode of operation associated with decreased power consumption in comparison to the light hibernation mode). While operating according to the light hibernation mode, the memory system may maintain a greater quantity of data in the volatile memory relative to the full hibernation mode, which may avoid at least some power consumption related to data transfers between the volatile memory and non-volatile memory that may occur in connection with entering and exiting the full hibernation mode.

公开(公告)号：US20250147660A1

公开(公告)日：2025-05-08

申请号：US19020409

申请日：2025-01-14

Applicant: Micron Technology, Inc.

Inventor： John D. Leidel

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G11C7/10 ,  G11C21/00

Abstract: An interconnect system includes host devices, one or more memory devices, and a routing system to connect the host devices and the one or more memory devices. Respective ones of the host devices include an interface to communicate packet requests over respective packetized links. Respective ones of the one or more memory devices include an interface to receive and respond to the packet requests over the respective packetized links. The routing system includes devices interconnected in a routing topology. Respective ones of the devices include a switch and interfaces. The routing system is to route the packet requests and responses between the host devices and respective memory device destinations over the respective packetized links. The host devices are to communicate cache coherency traffic to each other over at least one of the respective packetized links.

公开(公告)号：US12293798B2

公开(公告)日：2025-05-06

申请号：US17875827

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Meng Wei

IPC: G11C16/32 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34

Abstract: Disclosed herein are methods, apparatuses and systems related to adjusting operation of memory dies according to reliability measures determined in real-time. The apparatus may be configured to determine the reliability measures based on (1) initiating and completing a programming operation within respective timings following an erase operation and (2) reading the programmed data within a window from completing the programming operation.

公开(公告)号：US12293080B2

公开(公告)日：2025-05-06

申请号：US18233433

申请日：2023-08-14

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Caixia Yang

IPC: G06F12/00 ,  G06F3/06

Abstract: A memory sub-system to initiate an erase operation to erase a first set of memory cells of a first memory block and a second set of memory cells of a second memory block of a memory device. One or more erase pulses of the erase operation are caused to be applied to the first set of memory cells of the first memory block and the second set of memory cells of the second memory block concurrently. A first erase verify sub-operation of the erase operation is caused to be performed to verify the first memory block is erased and a second erase verify sub-operation of the erase operation is caused to be performed to verify the second memory block is erased.

公开(公告)号：US12292798B2

公开(公告)日：2025-05-06

申请号：US17822915

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G06F11/00 ,  G06F11/10

Abstract: Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.

公开(公告)号：US20250142839A1

公开(公告)日：2025-05-01

申请号：US18760921

申请日：2024-07-01

Applicant: Micron Technology, Inc.

Inventor： Marcello Mariani ,  Giorgio Servalli

IPC: H10B63/00 ,  H01L23/528 ,  H10N70/00

Abstract: A microelectronic device including first insulative structures, each first insulative structure including first sections individually having a first horizontal width in a first direction, and second sections horizontally alternating with the first sections in a second direction orthogonal to the first direction, the second sections individually having a second horizontal width in the first direction greater than the first width. First conductive structures are directly adjacent the first sections of the first insulative structures in the first direction and directly adjacent the second sections of the first insulative structures in the second direction. Second insulative structures are directly adjacent the first conductive structures and the second sections of the first insulative structures in the first direction; and second conductive structures are directly adjacent the second insulative structures in the first direction.

公开(公告)号：US20250142831A1

公开(公告)日：2025-05-01

申请号：US19004725

申请日：2024-12-30

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  David H. Wells ,  Umberto Maria Meotto

IPC: H10B43/50 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.