公开(公告)号：US20050264965A1

公开(公告)日：2005-12-01

申请号：US11142379

申请日：2005-06-02

申请人： Minoru Okamoto

发明人： Minoru Okamoto

IPC分类号： H01L23/12 ,  H01L21/822 ,  H01L23/60 ,  H01L27/04 ,  H02H9/00

CPC分类号： H01L23/60 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A semiconductor integrated circuit including a digital circuit and an analog circuit which are integrated on a single semiconductor chip comprises a first electrostatic destruction protection circuit, connected to a digital circuit, for protecting the digital circuit from destruction caused by ESD therein by an influence of an input digital signal and a second electrostatic destruction protection circuit, connected to an analog circuit, for protecting the analog circuit from destruction caused by ESD therein by an influence of an input analog signal. A first grounding conductor connected to the first electrostatic destruction protection circuit and a second grounding conductor connected to the second electrostatic destruction protection circuit are connected to each other outside the semiconductor integrated circuit.

摘要翻译： 包括集成在单个半导体芯片上的数字电路和模拟电路的半导体集成电路包括连接到数字电路的第一静电破坏保护电路，用于保护数字电路免受其中的ESD的影响， 输入数字信号和第二静电破坏保护电路，连接到模拟电路，用于通过输入模拟信号的影响来保护模拟电路免受其中的ESD的破坏。 连接到第一静电破坏保护电路的第一接地导体和连接到第二静电破坏保护电路的第二接地导体在半导体集成电路外部彼此连接。

公开(公告)号：US06735714B2

公开(公告)日：2004-05-11

申请号：US10252394

申请日：2002-09-24

申请人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Stone

发明人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Stone

IPC分类号： G06F1100

CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6561 ,  H03M13/6563 ,  H03M13/6569

摘要： A digital signal processor capable of performing a Viterbi algorithm is provided. The digital signal processor includes an instruction fetching unit that fetches instructions; a decoding unit that decodes the instructions fetched by the instruction fetching unit, and an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes a first comparing unit that compares first data with second data and a second comparing unit that compares third data with fourth data. The first comparing unit and the second comparing unit operate in parallel. Also, the first data, the second data, the third data, and the fourth data can each be one of four results obtained by adding one of two path metrics to one of two branch metrics. The execution unit outputs any two new path metrics in a high order position and a low order position respectively.

摘要翻译： 提供能够执行维特比算法的数字信号处理器。 数字信号处理器包括取指令的指令取出单元; 对由指令取出单元取出的指令进行解码的解码单元，以及执行由解码单元解码的指令的执行单元。 执行单元包括将第一数据与第二数据进行比较的第一比较单元和将第三数据与第四数据进行比较的第二比较单元。 第一比较单元和第二比较单元并行操作。 此外，第一数据，第二数据，第三数据和第四数据可以分别是通过将两个路径度量中的一个添加到两个分支度量之一而获得的四个结果之一。 执行单元分别在高阶位置和低位置输出任何两个新的路径度量。

公开(公告)号：US06450036B1

公开(公告)日：2002-09-17

申请号：US09554787

申请日：2000-12-11

申请人： Tetsuya Ashida ,  Tsuyoshi Ikeda ,  Junichiro Ikehara ,  Masanori Fujii ,  Hiroshi Ishibashi ,  Yoshiro Habuka ,  Minoru Okamoto ,  Eiji Onuma ,  Hiroshi Kato

发明人： Tetsuya Ashida ,  Tsuyoshi Ikeda ,  Junichiro Ikehara ,  Masanori Fujii ,  Hiroshi Ishibashi ,  Yoshiro Habuka ,  Minoru Okamoto ,  Eiji Onuma ,  Hiroshi Kato

IPC分类号： G01N2904

CPC分类号： G01N29/043 ,  G01N29/07 ,  G01N2291/011 ,  G01N2291/015 ,  G01N2291/0231 ,  G01N2291/0235 ,  G01N2291/0258 ,  G01N2291/0425 ,  G01N2291/102 ,  G01N2291/2626

摘要： The invention is directed to a method and apparatus for diagnosing deterioration of an article having at least a covering layer made from an organic polymer material. The method comprises (i) forming a data group for deterioration diagnosis comprising deterioration diagnostic characteristic values and corresponding ultrasonic wave propagation characteristic values for samples having different material specifications, (ii) propagating an ultrasonic wave through the covering layer of the article to measure an ultrasonic wave propagation characteristic of the covering layer, and (iii) determining a corresponding deterioration diagnostic characteristic from the data group for the ultrasonic wave propagation characteristic of the covering layer. The apparatus comprises (i) an ultrasonic wave propagation measuring device comprising an ultrasonic wave transmitting means, an ultrasonic wave receiving means, a delay chip, and a propagation time measuring means, (ii) a storage unit containing a data group for deterioration diagnosis, and (iii) a central processing unit.

摘要翻译： 本发明涉及用于诊断具有至少由有机聚合物材料制成的覆盖层的制品的劣化的方法和装置。 该方法包括：（i）形成用于劣化诊断的数据组，其包括具有不同材料规格的样品的劣化诊断特性值和相应的超声波传播特性值，（ii）将超声波传播通过制品的覆盖层以测量超声波 覆盖层的波传播特性，以及（iii）从覆盖层的超声波传播特性的数据组确定相应的恶化诊断特性。 该装置包括：（i）超声波传播测量装置，包括超声波发射装置，超声波接收装置，延迟芯片和传播时间测量装置，（ii）包含用于劣化诊断的数据组的存储单元， 和（iii）中央处理单元。

公开(公告)号：US06363469B1

公开(公告)日：2002-03-26

申请号：US09351733

申请日：1999-07-12

申请人： Minoru Okamoto ,  Hidetoshi Suzuki

发明人： Minoru Okamoto ,  Hidetoshi Suzuki

IPC分类号： G06F934

CPC分类号： G06F9/355 ,  G06F9/30101 ,  G06F9/345

摘要： An address generation apparatus for generating a first address and a second address includes a first register for storing a first reference address; a second register for storing a second reference address; a third register for storing a first offset value with respect to the first reference address, the first offset value being designated by an instruction; a fourth register for storing a second offset value with respect to the second reference address, the second offset value being designated by the instruction; a first adder for adding the first reference address stored in the first register and the first offset value stored in the third register; a second adder for adding the second reference address stored in the second register and the second offset value stored in the fourth register; a fifth register for storing an output from the first adder as the first address; and a sixth register for storing an output from the second adder as the second address.

摘要翻译： 一种用于产生第一地址和第二地址的地址产生装置包括用于存储第一参考地址的第一寄存器; 用于存储第二参考地址的第二寄存器; 第三寄存器，用于存储关于第一参考地址的第一偏移值，第一偏移值由指令指定; 第四寄存器，用于存储关于第二参考地址的第二偏移值，第二偏移值由指令指定; 第一加法器，用于将存储在第一寄存器中的第一参考地址和存储在第三寄存器中的第一偏移值相加; 第二加法器，用于将存储在第二寄存器中的第二参考地址和存储在第四寄存器中的第二偏移值相加; 第五寄存器，用于存储来自第一加法器的输出作为第一地址; 以及第六寄存器，用于存储来自第二加法器的输出作为第二地址。

公开(公告)号：US06266764B1

公开(公告)日：2001-07-24

申请号：US09271227

申请日：1999-03-17

申请人： Minoru Okamoto

发明人： Minoru Okamoto

IPC分类号： G06F930

CPC分类号： G06F9/3885 ,  G06F9/3851

摘要： A program controller for use in a processor operating on pipe-line principles includes: a first memory section for outputting an instruction contained in a first program including a plurality of instructions; a second memory section for outputting an instruction contained in a second program including a plurality of instructions, the first program being different from the second program; a selection section for selecting either the instruction which is output from the first memory section or the instruction which is output from the second memory section; a determination section for determining whether or not the instruction selected by the selection section is an instruction for controlling the execution order of instructions; and a control section for, if the instruction selected by the selection section is determined as an instruction for controlling the execution order of instructions, controlling the selection section so as to switch from the selected instruction to the unselected instruction of either the first memory section or the second memory section.

摘要翻译： 用于在管线原理上运行的处理器的程序控制器包括：第一存储器部分，用于输出包含在包括多个指令的第一程序中的指令; 第二存储器部分，用于输出包含在包括多个指令的第二程序中的指令，所述第一程序不同于所述第二程序; 选择部分，用于选择从第一存储器部分输出的指令或从第二存储器部分输出的指令; 确定部分，用于确定由选择部分选择的指令是否是用于控制指令的执行顺序的指令; 以及控制部分，如果由选择部分选择的指令被确定为用于控制指令的执行顺序的指令，则控制选择部分以便从所选择的指令切换到第一存储器部分或第一存储器部分的未选择指令 第二存储器部分。

公开(公告)号：US5537577A

公开(公告)日：1996-07-16

申请号：US58530

申请日：1993-05-06

申请人： Toshio Sugimura ,  Katsuhiko Ueda ,  Minoru Okamoto ,  Toshihiro Ishikawa ,  Mikako Yasutome

发明人： Toshio Sugimura ,  Katsuhiko Ueda ,  Minoru Okamoto ,  Toshihiro Ishikawa ,  Mikako Yasutome

IPC分类号： F02B75/02 ,  G06F12/06 ,  G06F12/00

CPC分类号： G06F12/0607 ,  F02B2075/025

摘要： An interleaving memory system having a first memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, a second memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, and a holding device for holding data from one of the banks of one of the first memory device and the second memory device to delay an output of the data for 1/2 cycle time for sequential addressing. A controller controls first and second selection devices wherein the 0-bank and the 1-bank are alternatively selected when data is outputted either in an ascending order of consecutive addresses from the even-numbered addresses in the first or second memory devices, or in a descending order of consecutive addresses from the odd-numbered addresses in the first or second memory devices. Also, the first holding device and a bank whose output is not held by the first holding device are alternatively selected when data is outputted either in a descending order of consecutive addresses from the even-numbered addresses in the first memory device, or in an ascending order of consecutive addresses from the odd-numbered addresses in the first memory device. The second holding device and a bank whose output is not held by the second holding device are similarly alternatively selected.

摘要翻译： 一种交织存储器系统，具有第一存储器装置，该第一存储器装置包括一个0组和一个一组，用于同时从该第一存储区输出来自0组的偶数地址的数据和奇数地址的数据;第二存储器装置 包括0行和1行，用于从0行同时从偶数行地址输出数据和来自1行的奇数地址的数据;以及保持装置，用于从一个存储体中的一个存储区中保存数据 第一存储器件和第二存储器件之一，用于将数据的输出延迟1/2个周期时间用于顺序寻址。 控制器控制第一和第二选择装置，其中当从第一或第二存储装置中的偶数地址以连续地址的升序输出数据时，交替地选择0组和1组，或者在 来自第一或第二存储器件中的奇数地址的连续地址的降序。 此外，当从第一存储装置中的偶数地址以连续地址的降序输出数据时，交替地选择第一保持装置和输出未被第一保持装置保持的存储体，或者以升序 来自第一存储设备中的奇数地址的连续地址的顺序。 类似地，第二保持装置和输出没有被第二保持装置保持的组。