公开(公告)号：US08093107B1

公开(公告)日：2012-01-10

申请号：US12271758

申请日：2008-11-14

Applicant: Farid Nemati ,  Scott Robins ,  Kevin J. Yang

Inventor： Farid Nemati ,  Scott Robins ,  Kevin J. Yang

IPC: H01L21/332 ,  H01L21/337 ,  H01L21/8238

CPC classification number: G11C11/39 ,  H01L27/1027 ,  H01L29/66393 ,  H01L29/7436

Abstract: A thyristor based semiconductor device includes a thyristor having cathode, P-base, N-base and anode regions disposed in electrical series relationship. The N-base region for the thyristor has a cross-section that defines an inverted “T” shape, wherein a buried well in semiconductor material forms is operable as a part of the N-base. The stem to the inverted “T” shape extends from the upper surface of the semiconductor material to the buried well. The P-base region for the thyristor extends laterally outward from a side of the stem that is opposite the anode region of the thyristor, and is further bounded between the buried well and a surface of the semiconductor material. A thinned portion for the N-base is defined between the cathode region of the thyristor and the buried well, and may include supplemental dopant of concentration greater than that for some other portion of the N-base.

Abstract translation: 一种基于晶闸管的半导体器件包括具有阴极，P基极，N基极和阳极区域的晶闸管，其以电串联的关系设置。 用于晶闸管的N基区域具有限定反向“T”形的横截面，其中半导体材料形式的掩埋阱可操作为N基底的一部分。 反向“T”形的杆从半导体材料的上表面延伸到掩埋井。 用于晶闸管的P基区域从杆的与晶闸管的阳极区域相对的侧面横向向外延伸，并且进一步限定在掩埋阱和半导体材料的表面之间。 在晶闸管的阴极区域和掩埋阱之间限定了用于N-碱的薄化部分，并且可以包括浓度大于N基底的其它部分浓度的补充掺杂剂。

公开(公告)号：US07858449B2

公开(公告)日：2010-12-28

申请号：US12367891

申请日：2009-02-09

Applicant: Kevin J. Yang ,  Farid Nemati ,  Scott Robins ,  James D. Plummer ,  Hyun-Jin Cho

Inventor： Kevin J. Yang ,  Farid Nemati ,  Scott Robins ,  James D. Plummer ,  Hyun-Jin Cho

IPC: H01L29/72

CPC classification number: G11C11/39 ,  H01L29/7436 ,  H01L29/749

Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.

Abstract translation: 在制造半导体存储器件的方法中，晶闸管可以形成在半导体材料层中。 可以在用于晶闸管的基极 - 发射极结区域中注入和退火碳以影响泄漏特性。 因此可以选择碳的密度和/或轰击能量和/或退火，以建立连接的低电压，泄漏特性，基本上大于其没有碳的泄漏。 在一个实施例中，注入碳的退火可以与半导体器件的其它注入区域的激活共同进行。

公开(公告)号：US07488626B1

公开(公告)日：2009-02-10

申请号：US11483859

申请日：2006-07-10

Applicant: Kevin J. Yang ,  Farid Nemati ,  Scott Robins ,  James D. Plummer ,  Hyun-Jin Cho

Inventor： Kevin J. Yang ,  Farid Nemati ,  Scott Robins ,  James D. Plummer ,  Hyun-Jin Cho

IPC: H01L29/72

CPC classification number: G11C11/39 ,  H01L29/7436 ,  H01L29/749

Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.

Abstract translation: 在制造半导体存储器件的方法中，晶闸管可以形成在半导体材料层中。 可以在用于晶闸管的基极 - 发射极结区域中注入和退火碳以影响泄漏特性。 因此可以选择碳的密度和/或轰击能量和/或退火，以建立连接的低电压，泄漏特性，基本上大于其没有碳的泄漏。 在一个实施例中，注入碳的退火可以与半导体器件的其它注入区域的激活共同进行。

公开(公告)号：US07054191B1

公开(公告)日：2006-05-30

申请号：US10860194

申请日：2004-06-03

Applicant: Rajesh Narendra Gupta ,  Scott Robins

Inventor： Rajesh Narendra Gupta ,  Scott Robins

IPC: G11C11/39 ,  G11C11/34

CPC classification number: G11C11/39

Abstract: A first and a second set of memory cells are connected to the same first word line and second word line. At the commencement of data writing, the first word line is set up. The first set of memory cells is read and temporarily stored into a buffer. At about the same time, the bit lines of the second set of memory cells is set up. After completion of reading of the first set of memory cells, the bit lines of this set of memory cells are set up (while the setting up of the bit lines of the second set of memory cells continues). After the bit lines of both sets of memory cells are set up, the second word line is pulsed. At this time, written into both sets of memory cells begins, which comprises data previously read from the first set of memory cells and new data to be written into the second set of memory cells. It is found that this method reduces the overall write time.

Abstract translation: 第一和第二组存储器单元连接到相同的第一字线和第二字线。 在数据写入开始时，第一个字线被设置。 第一组存储单元读取并临时存储到缓冲器中。 大约在同一时间，第二组存储器单元的位线被建立。 在完成第一组存储单元的读取之后，建立该组存储器单元的位线（同时第二组存储器单元的位线的设置继续）。 在两组存储器单元的位线被建立之后，第二字线被脉冲。 此时，开始写入两组存储器单元，其包括先前从第一组存储器单元读取的数据和要写入第二组存储器单元的新数据。 发现这种方法减少了整个写入时间。

公开(公告)号：US06998652B1

公开(公告)日：2006-02-14

申请号：US10262729

申请日：2002-10-01

Applicant: Andrew Horch ,  Scott Robins

Inventor： Andrew Horch ,  Scott Robins

IPC: H01L29/74 ,  H01L29/87

CPC classification number: H01L27/0629 ,  H01L27/0817 ,  H01L29/74

Abstract: A semiconductor device includes a thyristor body having at least one region in a substrate. According to an example embodiment of the present invention, a trench is in a substrate and adjacent to a thyristor body region in the substrate. The trench is lined with an insulative material and further includes conductive material that is insulated from the thyristor body region in the substrate by the liner material. A conductive thyristor control port is located in the trench and adapted for capacitively coupling to the thyristor body region in the substrate and to control current in the thyristor body by causing an outflow of minority carriers in the thyristor. With this approach, conductive material can be used to fill a portion of the trench while using the trench portion including the conductive material to electrically isolate a portion of the thyristor body in the substrate. This approach is particularly useful, for example, in high-density applications where insulative trenches having high aspect ratios are desired.

Abstract translation: 半导体器件包括在衬底中具有至少一个区域的晶闸管本体。 根据本发明的示例性实施例，沟槽在衬底中并且与衬底中的可控硅体区相邻。 沟槽衬有绝缘材料，并且还包括通过衬垫材料与衬底中的可控硅体区域绝缘​​的导电材料。 导电晶闸管控制端口位于沟槽中，适于电容耦合到衬底中的晶闸管本体区域，并通过引起晶闸管中少数载流子的流出来控制晶闸管主体中的电流。 利用这种方法，可以使用导电材料来填充沟槽的一部分，同时使用包括导电材料的沟槽部分来电隔离衬底中的可控硅体的一部分。 这种方法在例如需要具有高纵横比的绝缘沟槽的高密度应用中是特别有用的。

公开(公告)号：US06980457B1

公开(公告)日：2005-12-27

申请号：US10288927

申请日：2002-11-06

Applicant: Andrew Horch ,  Scott Robins

Inventor： Andrew Horch ,  Scott Robins

IPC: G11C11/39 ,  G11C17/06 ,  H01L27/102 ,  H01L27/105 ,  H01L27/108

CPC classification number: H01L27/105 ,  G11C11/39 ,  H01L27/1023 ,  H01L27/1027 ,  H01L27/108

Abstract: A thyristor-based semiconductor device is formed having a thyristor, a pass device and an emitter region buried in a substrate and below at least one other vertically-arranged contiguous region of the thyristor that is at least partially below an upper surface of the substrate. According to an example embodiment of the present invention, a conductor, such as a polysilicon pillar formed in a trench, extends through the substrate and to the buried emitter region of the thyristor. In one implementation, a portion of the conductor includes a reduced-resistance material, such as a salicide, that is adapted to reduce the resistance of an electrical connection made to the buried emitter region via the conductor. This is particularly useful, for example, in connecting the buried emitter region to a power supply at a reduced resistance (e.g., as compared to the resistance that would be exhibited, were the reduced-resistance material not present).

Abstract translation: 形成了一种晶闸管型半导体器件，其具有埋置在衬底中的晶闸管，通过器件和发射极区域，并且至少部分地在衬底的上表面下方的晶闸管的至少一个垂直布置的连续区域的下方。 根据本发明的示例性实施例，形成在沟槽中的诸如多晶硅柱的导体延伸穿过衬底和晶闸管的掩埋发射极区。 在一个实施方案中，导体的一部分包括抗电阻材料，例如自对准硅化物，其适于降低通过导体对掩埋发射极区域形成的电连接的电阻。 这特别有用，例如，以降低的电阻（例如，与所显示的电阻相比，不存在耐电阻材料）将掩埋的发射极区域连接到电源。

公开(公告)号：US06965129B1

公开(公告)日：2005-11-15

申请号：US10288953

申请日：2002-11-06

Applicant: Andrew Horch ,  Scott Robins ,  Farid Nemati

Inventor： Andrew Horch ,  Scott Robins ,  Farid Nemati

IPC: G11C11/39 ,  H01L21/8239 ,  H01L27/08 ,  H01L27/102 ,  H01L27/105 ,  H01L27/108 ,  H01L29/74

CPC classification number: G11C11/39 ,  H01L27/1025 ,  H01L27/1027 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L29/7436

Abstract: Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor having first and second base regions coupled between first and second emitter regions, respectively. A first control port capacitively couples a first signal to the first base region, and a second control port capacitively couples a second signal to the second base region. Each of the first and second signals have a charge that is opposite in polarity, and the opposite polarity signals effect the switching of the thyristor at a lower power, relative to the power that would be required to switch the thyristor having only one control port. In this manner, power consumption for a switching operation can be reduced, which is useful, for example, to correspond with reduced power supplied to other devices in a semiconductor device employing the thyristor.

Abstract translation: 使用适于在阻塞状态和导通状态之间切换的基于晶闸管的半导体器件来增强诸如存储器件中使用的切换操作。 根据本发明的示例性实施例，基于晶闸管的半导体器件包括分别具有耦合在第一和第二发射极区之间的第一和第二基极区域的晶闸管。 第一控制端口将第一信号电容耦合到第一基区，并且第二控制端口将第二信号电容耦合到第二基区。 第一和第二信号中的每一个具有极性相反的电荷，相反的极性信号相对于仅具有一个控制端口的晶闸管所需的功率，以较低的功率影响晶闸管的开关。 以这种方式，可以减少用于开关操作的功耗，这对于例如提供给采用晶闸管的半导体器件中的其它器件的降低的功率是有用的。

公开(公告)号：US06901021B1

公开(公告)日：2005-05-31

申请号：US10838595

申请日：2004-05-04

Applicant: Andrew Horch ,  Tapan Samaddar ,  Scott Robins

Inventor： Andrew Horch ,  Tapan Samaddar ,  Scott Robins

IPC: G11C7/14 ,  G11C7/00

CPC classification number: G11C7/14

Abstract: A reference cell produces a reference current that is about half of the current produced by a memory cell. The reference cell is essentially the same as the memory cell with an additional current reduction device that can be a transistor. Adjusting a reference voltage applied to the transistor allows the reference current to be varied. A control circuit to produce the reference voltage includes dedicated memory and reference cells and a feedback circuit that compares the two cell' currents. The feedback circuit applies the reference voltage to the reference cell of the control circuit and adjusts the reference voltage until the current from the reference cell is about half of th current from the memory cell. The reference voltage is then applied to other reference cells in a memory array.

Abstract translation: 参考单元产生约为由存储单元产生的电流的一半的参考电流。 参考单元基本上与具有可以是晶体管的附加电流减小器件的存储器单元相同。 调整施加到晶体管的参考电压允许参考电流变化。 用于产生参考电压的控制电路包括专用存储器和参考单元以及比较两个单元电流的反馈电路。 反馈电路将参考电压施加到控制电路的参考单元，并调整参考电压，直到来自参考单元的电流约为来自存储单元的电流的大约一半。 然后将参考电压施加到存储器阵列中的其它参考单元。

公开(公告)号：US06818482B1

公开(公告)日：2004-11-16

申请号：US10263370

申请日：2002-10-01

Applicant: Andrew Horch ,  Scott Robins

Inventor： Andrew Horch ,  Scott Robins

IPC: H01L21332

CPC classification number: H01L29/66363 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/0817 ,  H01L29/41716 ,  H01L29/749

Abstract: A semiconductor device includes a thyristor body having at least one region in a substrate. According to an example embodiment of the present invention, a trench is in a substrate and adjacent to a thyristor body region in the substrate. The trench is lined with an insulative material and further includes conductive material that is insulated from the thyristor body region in the substrate by the liner material. A conductive thyristor control port is located in the trench and adapted for capacitively coupling to the thyristor body region in the substrate and to control current in the thyristor body by causing an outflow of minority carriers in the thyristor. With this approach, conductive material can be used to fill a portion of the trench while using the trench portion including the conductive material to electrically isolate a portion of the thyristor body in the substrate. This approach is particularly useful, for example, in high-density applications where insulative trenches having high aspect ratios are desired.

Abstract translation: 半导体器件包括在衬底中具有至少一个区域的晶闸管本体。 根据本发明的示例性实施例，沟槽在衬底中并且与衬底中的可控硅体区相邻。 沟槽衬有绝缘材料，并且还包括通过衬垫材料与衬底中的可控硅体区域绝缘​​的导电材料。 导电晶闸管控制端口位于沟槽中，适于电容耦合到衬底中的晶闸管本体区域，并通过引起晶闸管中少数载流子的流出来控制晶闸管主体中的电流。 利用这种方法，可以使用导电材料来填充沟槽的一部分，同时使用包括导电材料的沟槽部分来电隔离衬底中的可控硅体的一部分。 这种方法在例如需要具有高纵横比的绝缘沟槽的高密度应用中是特别有用的。

公开(公告)号：US06686612B1

公开(公告)日：2004-02-03

申请号：US10263382

申请日：2002-10-01

Applicant: Andrew Horch ,  Scott Robins

Inventor： Andrew Horch ,  Scott Robins

IPC: H01L29423

CPC classification number: H01L27/0817 ,  H01L27/0629 ,  H01L29/87

Abstract: Parasitic current leakage from a thyristor-based semiconductor device is inhibited. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor body portion and a control port located in a substrate, the control port being adapted for capacitively coupling to the thyristor body portion for controlling current flow therein. The substrate further includes a doped circuit region separated by a channel region from another doped region of similar polarity in the substrate. The control port faces the channel region in the substrate, and the channel region is susceptible to current leakage in response to voltage pulses being applied to the control port for controlling current flow in the thyristor. The device is arranged such that such current leakage in the channel is inhibited while pulses are applied to the control port for controlling current flow in the thyristor; the parasitic current leakage between the doped circuit region and the doped region in the substrate is inhibited.

Abstract translation: 抑制了基于晶闸管的半导体器件的寄生电流泄漏。 根据本发明的一个示例性实施例，一种基于晶闸管的半导体器件包括晶闸管主体部分和位于衬底中的控制端口，该控制端口适于与晶闸管主体部分电容耦合以控制其中的电流流动。 衬底还包括由衬底中具有相似极性的另一个掺杂区域的沟道区域分离的掺杂电路区域。 控制端口面向衬底中的沟道区域，并且响应于施加到控制端口的电压脉冲来控制电流流过晶闸管，沟道区域容易受到电流泄漏。 该装置被布置为使得在控制端口处施加脉冲以控制晶闸管中的电流流动时，通道中的这种电流泄漏被抑制; 抑制了衬底中的掺杂电路区域和掺杂区域之间的寄生电流泄漏。