公开(公告)号：US12183626B2

公开(公告)日：2024-12-31

申请号：US17883647

申请日：2022-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-How Chou ,  Tzu-Hao Fu ,  Tsung-Yin Hsieh ,  Chih-Sheng Chang ,  Shih-Chun Tsai ,  Kun-Chen Ho ,  Yang-Chou Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.

公开(公告)号：US20240429316A1

公开(公告)日：2024-12-26

申请号：US18822485

申请日：2024-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jhe Hsu ,  Che-Yi Ho

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165

Abstract: A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, a second buffer layer on the first buffer layer, a bulk layer on the second buffer layer, a first cap layer on the bulk layer, and a second cap layer on the first cap layer. Preferably, the bottom surface of the first buffer layer includes a linear surface, a bottom surface of the second buffer layer includes a curve, and the second buffer layer includes a linear sidewall.

公开(公告)号：US12178052B2

公开(公告)日：2024-12-24

申请号：US17368848

申请日：2021-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Wu ,  Cheng-Tung Huang ,  Jen-Yu Wang ,  Yung-Ching Hsieh ,  Po-Chun Yang ,  Jian-Jhong Chen ,  Bo-Chang Li

IPC: H10B61/00 ,  H10N50/80

Abstract: A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.

公开(公告)号：US12176800B2

公开(公告)日：2024-12-24

申请号：US18081706

申请日：2022-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiu-Ming Yeh ,  Min-Chia Wang

IPC: H02M1/00 ,  H02M3/155

Abstract: A current generator includes a startup circuit and a bandgap reference circuit coupled to the startup circuit. The startup circuit is for generating a first voltage. The bandgap reference circuit is for generating a second voltage. The bandgap reference circuit includes an operational amplifier. The operational amplifier includes a bias source circuit and a bias generator circuit. The bias source circuit is for generating a reference current according to the first voltage and the second voltage. The bias generator circuit is for generating bias voltages according to the reference current. The startup circuit and the bandgap reference circuit receive a supply voltage.

公开(公告)号：US20240422989A1

公开(公告)日：2024-12-19

申请号：US18223043

申请日：2023-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

Abstract: A resistive memory device includes a dielectric layer, a trench, a first resistive switching element, a diode via structure, and a signal line structure. The trench is disposed in the dielectric layer. The first resistive switching element is disposed in the trench. The first resistive switching element includes a first bottom electrode, a first top electrode disposed above the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode. The diode via structure is disposed in the dielectric layer and located under the trench, and the diode via structure is connected with the first bottom electrode. The signal line structure is disposed in the trench, a part of the signal line structure is disposed on the first resistive switching element, and the signal line structure is electrically connected with the first top electrode.

公开(公告)号：US20240413225A1

公开(公告)日：2024-12-12

申请号：US18811736

申请日：2024-08-21

Applicant: UNITED MICROELECTRONICS CORP

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/66 ,  H01L21/762

Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

公开(公告)号：US20240413199A1

公开(公告)日：2024-12-12

申请号：US18811821

申请日：2024-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Chuang-Han Hsieh ,  Kai-Lin Lee

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/51 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.

公开(公告)号：US20240413136A1

公开(公告)日：2024-12-12

申请号：US18223539

申请日：2023-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Kai Yu ,  Chen-Hsiao Wang ,  Yi-Feng Hsu ,  Kai-Kuang Ho

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

Abstract: The present invention provides a 3D integrated circuit structure formed by stacking semiconductor structures. The semiconductor structures form a multi-die heterogeneous 3D packaging by direct bonding the bonding pads of re-distribution layers. The same or different dies are used to produce the semiconductor structures through the back-end packaging process, and then hybrid bonding technology is used to stack and interconnect the semiconductor structures. The position of the bonding pad can be redefined by re-distribution layer, thereby overcoming the limitations of chip bonding pad position, chip size and quantity.

公开(公告)号：US20240413106A1

公开(公告)日：2024-12-12

申请号：US18350755

申请日：2023-07-12

Applicant: United Microelectronics Corp.

Inventor： Chien-Ming Lai

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor device includes a substrate, a bonding structure and an adjustment layer. A bonding structure is located over the substrate. The adjustment layer is located on a bonding pad of the bonding structure.

公开(公告)号：US20240407274A1

公开(公告)日：2024-12-05

申请号：US18219717

申请日：2023-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

Abstract: A resistive switching device includes a substrate; a first dielectric layer on the substrate; a conductive via in the first dielectric layer; a bottom electrode on the conductive via and the first dielectric layer, a resistive switching layer on the bottom electrode; and a cone-shaped top electrode on the resistive switching layer. The cone-shaped top electrode can produce increased and concentrated electric field during operation, which facilitates the filament forming process.