公开(公告)号：US20050080961A1

公开(公告)日：2005-04-14

申请号：US10682571

申请日：2003-10-09

Applicant: Ryan Bedwell ,  Arnaldo Cruz ,  John Vaglica ,  William Moyer

Inventor： Ryan Bedwell ,  Arnaldo Cruz ,  John Vaglica ,  William Moyer

IPC: G06F20060101 ,  G06F13/36 ,  G06F13/364

CPC classification number: G06F13/364

Abstract: New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.

公开(公告)号：US5638905A

公开(公告)日：1997-06-17

申请号：US242730

申请日：1994-05-12

Applicant: Robert D. Sigafoos ,  William Moyer ,  Mary Hazzard

Inventor： Robert D. Sigafoos ,  William Moyer ,  Mary Hazzard

IPC: A01L15/00 ,  A01K13/00 ,  A01L3/00 ,  A01L5/00 ,  A01L7/00

CPC classification number: A01L5/00 ,  A01K13/007 ,  A01L3/00 ,  A01L7/00

Abstract: A protective covering for a horse's hoof which comprises a horseshoe having convex and concave edges and a skirt embedded in a polymeric resin bonded to the horseshoe and extending beyond the convex edge of the horseshoe. The skirt may be made from any suitable flexible sheet material including a polymeric fiber fabric, a molded thermoplastic sheet material, or a laminate of molded thermoplastic sheet material and polymeric fiber fabric. When the shoe is fitted to the horse's hoof, the skirt extends up over the outside of the hoof. The protective covering is secured to the hoof using an acrylic structural adhesive both between the hoof and the shoe and between the skirt and the outside of the hoof. The skirt is preferably a thermoplastic acrylonitrile-butadiene-styrene. The polymeric resin is preferably polyurethane.

Abstract translation: 马蹄的防护罩，其包括具有凸形和凹形边缘的马蹄铁，以及镶嵌在结合到马掌上并延伸超过马蹄形凸起边缘的聚合物树脂中的裙部。 裙部可以由任何合适的柔性片材制成，包括聚合物纤维织物，模制的热塑性片材材料或模制的热塑性片材和聚合物纤维织物的层压材料。 当鞋子安装到马的蹄上时，裙子向上延伸到蹄外部。 使用丙烯酸结构粘合剂将保护性覆盖物固定在蹄上，蹄和鞋之间以及裙部和蹄外部之间。 裙部优选为热塑性丙烯腈 - 丁二烯 - 苯乙烯。 聚合物树脂优选为聚氨酯。

公开(公告)号：US20070260950A1

公开(公告)日：2007-11-08

申请号：US11355681

申请日：2006-02-16

Applicant: Gary Morrison ,  Jose Lyon ,  William Moyer ,  Anthony Reipold

Inventor： Gary Morrison ,  Jose Lyon ,  William Moyer ,  Anthony Reipold

IPC: G01R31/28

CPC classification number: G01R31/318544 ,  G01R31/318536 ,  G01R31/318552 ,  G06F11/2236

Abstract: A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor. The method further includes applying a test stimulus for testing the at least one logic block of the processor. The test stimulus may be shifted into scan chains so as to perform scan testing of the processor during normal operation, such as during execution of a user application.

Abstract translation: 用于测试处理器的至少一个逻辑块的方法包括在处理器执行用户应用期间，处理器产生停止和测试指示符。 响应于产生停止和测试指示符，停止执行用户应用程序，并且如果需要，保存处理器的至少一个逻辑块的状态。 该方法还包括应用用于测试处理器的至少一个逻辑块的测试激励。 测试刺激可以被转移到扫描链中，以便在正常操作期间，例如在用户应用的执行期间执行处理器的扫描测试。

公开(公告)号：US20070255933A1

公开(公告)日：2007-11-01

申请号：US11413255

申请日：2006-04-28

Applicant: William Moyer

Inventor： William Moyer

IPC: G06F9/44

CPC classification number: G06F9/30094 ,  G06F9/30036

Abstract: A processing system and method performs data processing operations in response to a single data processing instruction. At least two registers store data. First control circuitry compares data in respective corresponding fields of the at least two registers to create a plurality of condition values. Second control circuitry performs one or more predetermined logic operations on less than all of the plurality of condition values and on more than one condition value of the plurality of condition values to generate a condition code for each of the one or more predetermined logic operations. A condition code register stores the condition code for each of the one or more predetermined logic operations.

Abstract translation: 处理系统和方法响应于单个数据处理指令执行数据处理操作。 至少两个寄存器存储数据。 第一控制电路比较至少两个寄存器的相应对应字段中的数据，以创建多个条件值。 第二控制电路在少于所有多个条件值中的多个条件值的多于一个状态值上执行一个或多个预定逻辑运算，以生成一个或多个预定逻辑运算中的每个条件值的条件代码。 条件码寄存器存储一个或多个预定逻辑运算中的每一个的条件码。

公开(公告)号：US20070239968A1

公开(公告)日：2007-10-11

申请号：US11278725

申请日：2006-04-05

Applicant: William Moyer ,  Imran Ahmed ,  Dan Tamir

Inventor： William Moyer ,  Imran Ahmed ,  Dan Tamir

IPC: G06F9/44

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30101

Abstract: A method for operating a data processing system is provided. The method includes providing a first operand stored in a first register, providing a second operand stored in the register, providing a third operand stored in the register. The method further includes executing a first instruction, where executing the first instruction comprises: (1) retrieving the first operand, the second operand, and the third operand from the first register; (2) performing an operation using the first operand, the second operand, and the third operand to generate a bit exact result.

Abstract translation: 提供了一种操作数据处理系统的方法。 该方法包括提供存储在第一寄存器中的第一操作数，提供存储在寄存器中的第二操作数，提供存储在寄存器中的第三操作数。 该方法还包括执行第一指令，其中执行第一指令包括：（1）从第一寄存器检索第一操作数，第二操作数和第三操作数; （2）使用第一操作数，第二操作数和第三操作数执行操作以产生比特精确的结果。

公开(公告)号：US20070186217A1

公开(公告)日：2007-08-09

申请号：US11347103

申请日：2006-02-03

Applicant: Brett Murdock ,  William Moyer ,  Benjamin Eckermann

Inventor： Brett Murdock ,  William Moyer ,  Benjamin Eckermann

IPC: G06F9/46

CPC classification number: G06F13/14 ,  G06F13/36

Abstract: A method includes receiving, at an interconnect, a first transaction request from a first requesting module. The first transaction request includes a request to utilize at least one system resource accessible via the interconnect. The method further includes determining potential interferences at the interconnect expected to occur as a result of a utilization of the at least one system resource by the first requesting module and initiating processing of the first transaction request at the interconnect. The method additionally includes authorizing processing of a second transaction request from a second requesting module during the processing of the first transaction request based on the determined potential interferences.

Abstract translation: 一种方法包括在互连处从第一请求模块接收第一事务请求。 第一交易请求包括利用经由互连可访问的至少一个系统资源的请求。 该方法还包括确定作为由第一请求模块利用至少一个系统资源并且在互连处开始处理第一事务请求的结果期望发生的互连处的潜在干扰。 该方法另外包括基于所确定的潜在干扰，在第一交易请求的处理期间授权处理来自第二请求模块的第二交易请求。

公开(公告)号：US20060277349A1

公开(公告)日：2006-12-07

申请号：US11142148

申请日：2005-06-01

Applicant: Brett Murdock ,  William Moyer ,  Michael Fitzsimmons

Inventor： Brett Murdock ,  William Moyer ,  Michael Fitzsimmons

IPC: G06F13/00

CPC classification number: G06F13/4022

Abstract: A method is disclosed whereby a priority amongst transactions capable of being processed at a common time is determined based upon a transaction identifier associated with each of the transaction. The transaction identifier can either directly indicate a priority amongst the transactions, or use to index storage locations that indicate priority values. The transaction identifiers can be selected to be associated with a transaction by the requesting device or other priority determination module based upon predefined criteria.

Abstract translation: 公开了一种方法，其中基于与每个交易相关联的交易标识符来确定能够在公共时间处理的交易中的优先级。 事务标识符可以直接指示事务之间的优先级，或用于索引指示优先级值的存储位置。 可以基于预定义的标准，将请求设备或其他优先级确定模块的交易标识符选择为与交易相关联。

公开(公告)号：US20060271759A1

公开(公告)日：2006-11-30

申请号：US11140176

申请日：2005-05-27

Applicant: William Moyer

Inventor： William Moyer

IPC: G06F12/00

CPC classification number: G06F12/1027

Abstract: A system for obtaining translation information from a data processing system. The system includes circuitry for receiving an external request for translation information. The circuitry determines whether the requested translation information is present in memory management circuitry of a data processing system. If the translation information is not present in the memory management circuitry, the circuitry requests retrieval of the information by a processor core. In one embodiment, the request is performed by generating an interrupt to the processor core. In other embodiments, the request is preformed by requesting the activation a program thread to be executed by the processor core.

Abstract translation: 一种用于从数据处理系统获得翻译信息的系统。 该系统包括用于接收翻译信息的外部请求的电路。 电路确定所请求的翻译信息是否存在于数据处理系统的存储器管理电路中。 如果翻译信息不存在于存储器管理电路中，则电路请求由处理器核心检索信息。 在一个实施例中，通过向处理器核产生中断来执行该请求。 在其他实施例中，请求通过请求激活要由处理器核执行的程序线程来执行。

公开(公告)号：US20060069839A1

公开(公告)日：2006-03-30

申请号：US10955558

申请日：2004-09-30

Applicant: William Moyer ,  Brett Murdock

Inventor： William Moyer ,  Brett Murdock

IPC: G06F13/36

CPC classification number: G06F13/368

Abstract: A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

公开(公告)号：US20060053256A1

公开(公告)日：2006-03-09

申请号：US10631136

申请日：2004-09-09

Applicant: William Moyer ,  Lea Lee ,  Afzal Malik

Inventor： William Moyer ,  Lea Lee ,  Afzal Malik

IPC: G06F12/00

CPC classification number: G06F12/0215 ,  Y02D10/13

Abstract: In one embodiment, a data processing system (10) includes a first master, storage circuitry (35) coupled to the first master (12) for use by the first master (12), a first control storage circuit (38) which stores a first prefetch limit (60), a prefetch buffer (42), and prefetch circuitry (40) coupled to the first control storage circuit, to the prefetch buffer, and to the storage circuitry. In one embodiment, the prefetch circuitry (40) selectively prefetches a predetermined number of lines from the storage circuitry into the prefetch buffer (42) based on whether or not a prefetch counter, initially set to a value indicated by the first prefetch limit, has expired. In one embodiment, the first prefetch limit may therefore be used to control how many prefetches occur between misses in the prefetch buffer.

Abstract translation: 在一个实施例中，数据处理系统（10）包括第一主机，耦合到第一主机（12）以供第一主机（12）使用的存储电路（35），第一控制存储电路（38） 第一预取限制（60），预取缓冲器（42）和耦合到第一控制存储电路的预取电路（40）到预取缓冲器以及存储电路。 在一个实施例中，预取电路（40）基于是否初始设置为由第一预取限制指示的值的预取计数器是否具有预取数计数器（40）具有预定数量的行从存储电路到预取缓冲器（42） 已过期 在一个实施例中，因此可以使用第一预取限制来控制在预取缓冲器中的未命中之间发生多少个预取。