公开(公告)号：US08773922B2

公开(公告)日：2014-07-08

申请号：US12614545

申请日：2009-11-09

Applicant: Seung-Hwan Song ,  Jaehong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Jun Jin Kong ,  Jong Han Kim

Inventor： Seung-Hwan Song ,  Jaehong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Jun Jin Kong ,  Jong Han Kim

IPC: G11C7/06

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C29/00 ,  G11C2211/5634

Abstract: A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit.

Abstract translation: 公开了一种非易失性半导体存储器件及确定读取电压的相关方法。 非易失性半导体存储器件包括： 包括多个存储单元的存储单元阵列，读电压确定单元，被配置为通过将在编程操作期间获得的参考数据与在随后的读取操作期间获得的比较数据进行比较来确定最佳读取电压，并将当前读取电压改变为新的 基于比较结果的读取电压和读取电压生成单元，被配置为响应于由读取电压确定单元提供的读取电压控制信号而产生新的读取电压。

公开(公告)号：US08711624B2

公开(公告)日：2014-04-29

申请号：US13236249

申请日：2011-09-19

Applicant: Seonghyeog Choi ,  Hong Rak Son ,  Junjin Kong ,  Jaehong Kim ,  KyoungLae Cho ,  Yong June Kim

Inventor： Seonghyeog Choi ,  Hong Rak Son ,  Junjin Kong ,  Jaehong Kim ,  KyoungLae Cho ,  Yong June Kim

IPC: G11C11/34

CPC classification number: G11C11/5621 ,  G11C16/10 ,  G11C16/3404

Abstract: A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array.

Abstract translation: 存储器装置包括存储单元阵列，配置成使用交织方案将数据进行交错和加载到缓冲电路中的自交织器以及被配置为控制对存储单元阵列中的交错数据的编程的控制逻辑。

公开(公告)号：US08473668B2

公开(公告)日：2013-06-25

申请号：US12379273

申请日：2009-02-18

Applicant: Yong June Kim ,  Jae Hong Kim ,  Kyoung Lae Cho ,  Jun Jin Kong

Inventor： Yong June Kim ,  Jae Hong Kim ,  Kyoung Lae Cho ,  Jun Jin Kong

IPC: G06F12/00

CPC classification number: G11C16/349 ,  G11C11/5628 ,  G11C2211/5644

Abstract: The memory device selects any one of a first memory cell and a second memory cell based on a number of times that the first memory cell is erased, an elapsed time after the first memory cell is erased, a number of times that the second memory cell is erased, and an elapsed time after the second memory cell is erased, and program data in the selected memory cell. The memory device may improve distribution of threshold voltage of memory cells and endurance of the memory cells.

Abstract translation: 存储装置基于第一存储单元的擦除次数，第一存储单元被擦除后的经过时间，第二存储单元的次数，选择第一存储单元和第二存储单元中的任一个， 被擦除，并且第二存储单元被擦除之后的经过时间，以及所选存储单元中的程序数据。 存储器件可以改善存储器单元的阈值电压分布和存储单元的耐久性。

公开(公告)号：US08413011B2

公开(公告)日：2013-04-02

申请号：US12651586

申请日：2010-01-04

Applicant: Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong

Inventor： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong

IPC: H03M13/00

CPC classification number: G06F11/1008 ,  H03M13/1105 ,  H03M13/1108

Abstract: A 1-bit error correction method is provided. In the method, a variable node at which an error has occurred is detected based on a number of unsatisfied check nodes that do not satisfy a parity condition among check nodes connected to each of variable nodes and an error in a bit corresponding to the detected variable node is corrected.

Abstract translation: 提供1位纠错方法。 在该方法中，基于在连接到每个可变节点的校验节点中不满足奇偶校验条件的不满足校验节点的数量和对应于检测变量的位的错误来检测发生错误的变量节点 节点被更正。

公开(公告)号：US08370710B2

公开(公告)日：2013-02-05

申请号：US12507096

申请日：2009-07-22

Applicant: Yong June Kim ,  Jaehong Kim ,  Junjin Kong

Inventor： Yong June Kim ,  Jaehong Kim ,  Junjin Kong

IPC: G11C29/00

CPC classification number: H03M13/373 ,  G06F11/1068 ,  H03M13/13 ,  H03M13/455

Abstract: Provided are data processing methods for a non-volatile memory. The data processing methods include obtaining read data and erasure information from the non-volatile memory and correcting an error in the read data by referencing the erasure information obtained from the non-volatile memory. Memory systems may be provided. Such memory systems may include a non-volatile memory and a memory controller that is operable to perform an error correction operation according to the methods described herein.

Abstract translation: 提供了用于非易失性存储器的数据处理方法。 数据处理方法包括从非易失性存储器获取读取数据和擦除信息，并通过参考从非易失性存储器获取的擦除信息来校正读取数据中的错误。 可以提供存储器系统。 这样的存储器系统可以包括非易失性存储器和可操作以根据本文所述的方法执行纠错操作的存储器控​​制器。

公开(公告)号：US20130007081A1

公开(公告)日：2013-01-03

申请号：US13537297

申请日：2012-06-29

Applicant: KI JUN LEE ,  JUN JIN KONG ,  YONG JUNE KIM ,  JAE HONG KIM ,  HONG RAK SON ,  JUNG SOO CHUNG ,  SEONG HYEONG CHOI

Inventor： KI JUN LEE ,  JUN JIN KONG ,  YONG JUNE KIM ,  JAE HONG KIM ,  HONG RAK SON ,  JUNG SOO CHUNG ,  SEONG HYEONG CHOI

IPC: G06F7/58

CPC classification number: G06F7/584 ,  G06F2207/583

Abstract: A data processing which includes a conversion circuit and a pseudo random number generator including a series connection of plural shift registers. The conversion circuit receives a pseudo random number sequence from an output of one of the plural shift registers excluding a last shift register of the series connection, and converts first data to second data using the received pseudo random number sequence.

Abstract translation: 一种包括转换电路和包括多个移位寄存器的串联连接的伪随机数发生器的数据处理。 转换电路从除串行连接的最后一个移位寄存器之外的多个移位寄存器中的一个的输出接收伪随机数序列，并且使用接收到的伪随机数序列将第一数据转换为第二数据。

公开(公告)号：US08339846B2

公开(公告)日：2012-12-25

申请号：US12856698

申请日：2010-08-16

Applicant: Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

Inventor： Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642

Abstract: The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.

Abstract translation: 闪存器件包括控制逻辑电路和位电平转换逻辑电路。 控制逻辑电路对N位MLC闪速存储器件的存储单元阵列中的第一至第N位数据进行编程，或响应于程序命令和程序命令之一从存储单元阵列中读取数据的第一至第N位 读命令。 在数据的第一至第N位被完全编程或读取之后，位电平转换控制逻辑电路响应于控制信号编程或读取数据的第（N + 1）位。 位电平转换控制逻辑电路转换用于编程或读取数据的第一至第N位的电压电平，以对与第（N + 1）个对应的2N + 1个单元分布的2N个单元分布进行编程或读取 ）位，然后编程或读取其他2N个单元分布。

公开(公告)号：US08316279B2

公开(公告)日：2012-11-20

申请号：US12607768

申请日：2009-10-28

Applicant: Jaehong Kim ,  Yong June Kim ,  Seung Hwan Song

Inventor： Jaehong Kim ,  Yong June Kim ,  Seung Hwan Song

IPC: G11C29/00

CPC classification number: H03M13/1108 ,  G06F11/1072

Abstract: A method, implemented by at least an error correction code (ECC) decoder and a controller, estimates and corrects errors in memory cells. The method includes identifying a first candidate group of memory cells having an error-generation possibility using a first method for error estimation; identifying a second candidate group of memory cells having an error-generation possibility using a second method for error estimation; and correcting errors in at least one cell commonly included in the first and second candidate groups.

Abstract translation: 至少由纠错码（ECC）解码器和控制器实施的方法估计并校正存储器单元中的错误。 该方法包括使用第一种误差估计方法来识别具有错误产生可能性的存储器单元的第一候选组; 使用用于错误估计的第二方法识别具有错误生成可能性的第二候选组存储器单元; 以及校正通常包括在第一和第二候选组中的至少一个单元中的错误。

公开(公告)号：US20120290783A1

公开(公告)日：2012-11-15

申请号：US13467255

申请日：2012-05-09

Applicant: Jung Soo CHUNG ,  Yong June KIM ,  Jun Jin KONG ,  Hongrak SON

Inventor： Jung Soo CHUNG ,  Yong June KIM ,  Jun Jin KONG ,  Hongrak SON

IPC: G06F12/00

CPC classification number: G11C7/1006 ,  G11C7/1012 ,  G11C11/5628 ,  G11C16/0483

Abstract: A memory device including a randomizer and a memory system including the memory device are provided. The memory device includes: a randomizer including a sequence generator which generates a first sequence from a seed and a converter which converts the first sequence into a second sequence in response to a conversion factor, the randomizer randomizing data to be programmed using the second sequence and outputting the randomized data; and a storage area which receives the randomized data from the randomizer and storing the randomized data.

Abstract translation: 提供了包括随机化器和包括存储器件的存储器系统的存储器件。 存储装置包括：随机化器，其包括从种子生成第一序列的序列发生器和响应于转换因子将第一序列转换为第二序列的转换器，随机化器使用第二序列随机化要编程的数据，以及 输出随机数据; 以及存储区域，其从随机化器接收随机数据并存储随机数据。

公开(公告)号：US20120233518A1

公开(公告)日：2012-09-13

申请号：US13414002

申请日：2012-03-07

Applicant: Kijun Lee ,  Junjin Kong ,  Sejin Lim ,  Jaehong Kim ,  Hong-Rak Son ,  Yong-June Kim

Inventor： Kijun Lee ,  Junjin Kong ,  Sejin Lim ,  Jaehong Kim ,  Hong-Rak Son ,  Yong-June Kim

IPC: H03M13/29 ,  G06F11/10

CPC classification number: H03M13/2906 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2933 ,  H03M13/2957 ,  H03M13/3738

Abstract: A method may be provided to detect and correct data errors in a data system where a data message has been encoded with outer parity bits based on the data message using an outer encoding technique to provide an outer codeword and with inner parity bits based on the outer codeword using an inner encoding technique different than the outer encoding technique to provide an inner codeword. The method may include using the inner parity bits and an inner decoding technique corresponding to the inner encoding technique to perform inner decoding of the inner codeword. Responsive to performing inner decoding of the inner codeword without error, the data message may be extracted from a result of inner decoding the inner codeword without using the outer parity bits to decode the result of inner decoding the inner codeword. Related systems are also discussed.

Abstract translation: 可以提供一种方法来检测和校正数据系统中的数据错误，其中数据消息已经使用外部奇偶校验比特基于数据消息使用外部编码技术进行编码，以提供外部码字，并且具有基于外部奇偶校验位的内部奇偶校验位 码字使用与外部编码技术不同的内部编码技术来提供内部码字。 该方法可以包括使用内部奇偶校验位和对应于内部编码技术的内部解码技术来执行内部码字的内部解码。 响应于无误地执行内部码字的内部解码，可以从内部码字的内部解码的结果中提取数据消息，而不使用外部奇偶校验位来解码内​​部码字的内部解码结果。 还讨论了相关系统。