公开(公告)号：US20180286495A1

公开(公告)日：2018-10-04

申请号：US15475670

申请日：2017-03-31

申请人： Eun Chu OH ,  Pilsang YOON ,  Jun Jin KONG ,  Hong Rak SON ,  Dongsup JIN

发明人： Eun Chu OH ,  Pilsang YOON ,  Jun Jin KONG ,  Hong Rak SON ,  Dongsup JIN

IPC分类号： G11C29/50 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10

CPC分类号： G11C29/50004 ,  G11C11/5642 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5004

摘要： A nonvolatile memory storage system includes a plurality of memory cells and a memory controller configured to transmit a read command to a nonvolatile memory device based on a plurality of read voltages. The nonvolatile memory device performs a first read operation on a first level among the N levels based on a first read voltage among the plurality of read voltages, counts the number of on-cells that respond to the first read voltage among the plurality of memory cells, and adjusts a level of a second read voltage to be used to perform a second read operation on the first level or a second level among the N levels among the plurality of read voltages according to a comparison result of the counted number of on-cells and the number of reference cells.

公开(公告)号：US20160217030A1

公开(公告)日：2016-07-28

申请号：US15001012

申请日：2016-01-19

申请人： DONG-MIN SHIN ,  JUN-JIN KONG ,  BEOM-KYU SHIN ,  EUN-CHU OH ,  PIL-SANG YOON

发明人： DONG-MIN SHIN ,  JUN-JIN KONG ,  BEOM-KYU SHIN ,  EUN-CHU OH ,  PIL-SANG YOON

IPC分类号： G06F11/08 ,  G06F11/10

CPC分类号： G06F11/085 ,  G06F11/1012 ,  G06F11/1048 ,  H03M13/00 ,  H03M13/1102 ,  H03M13/1162 ,  H03M13/1165 ,  H03M13/1174 ,  H03M13/1182 ,  H03M13/255

摘要： A method of operating a memory system includes receiving information data corresponding to a second program unit that is a part of a first program unit and a write request for the information data from a host; generating a codeword by performing error correction code (ECC) encoding on the received information data such that a partial parity bit corresponding to the information data among all parity bits of the codeword is updated; and providing a memory device with the generated codeword and a write command regarding the codeword.

摘要翻译： 操作存储器系统的方法包括从主机接收与作为第一程序单元的一部分的第二程序单元相对应的信息数据和对信息数据的写入请求; 通过对接收到的信息数据执行纠错码（ECC）编码来生成码字，使得与码字的所有奇偶校验位之间的信息数据相对应的部分奇偶校验位被更新; 以及提供具有生成的码字的存储器装置和关于码字的写入命令。

公开(公告)号：US09069714B2

公开(公告)日：2015-06-30

申请号：US13606551

申请日：2012-09-07

申请人： Hak-Soo Yu ,  Jun-Jin Kong ,  Hyoung-Joon Kim ,  Joo-Young Hwang ,  In-Su Choi

发明人： Hak-Soo Yu ,  Jun-Jin Kong ,  Hyoung-Joon Kim ,  Joo-Young Hwang ,  In-Su Choi

IPC分类号： G06F13/14 ,  G06F13/16 ,  G06F13/38

CPC分类号： G06F13/16 ,  G06F13/1694 ,  G06F13/385

摘要： A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit.

摘要翻译： 设备包括存储器控制器，耦合到存储器控制器的存储器总线，内部存储器和外部存储器连接单元。 内部存储器可以通过存储器总线直接连接到存储器控制器。 外部存储器连接单元可以通过存储器总线中的一部分信号线将外部存储器直接连接到存储器控制器，并且可以产生指示外部存储器是否连接到外部存储器连接单元的标志信号。

公开(公告)号：US08984036B2

公开(公告)日：2015-03-17

申请号：US13547212

申请日：2012-07-12

申请人： Yong June Kim ,  Jung Soo Chung ,  Jun Jin Kong ,  Hongrak Son

发明人： Yong June Kim ,  Jung Soo Chung ,  Jun Jin Kong ,  Hongrak Son

IPC分类号： G06F7/58

CPC分类号： G06F7/582

摘要： A method for operating a controller may include storing a pseudo noise (PN) sequence provided from a PN sequence generator in an i-th area of a seed table and cyclically shifting the PN sequence from the i-th area to an (i+1)-th area in the table to form the table. The table may include row and column areas. A method for operating a controller may include receiving a sequence from a sequence generator, splitting the sequence into seed units, storing split sequences in a j-th area of the seed table, and forming the table including the seed units corresponding to the split sequences stored in the j-th area. A method for operating a controller may include storing a sequence provided from a sequence generator in a seed table that includes a plurality of areas and cyclically shifting the sequence in the table until a seed is formed in each area.

摘要翻译： 用于操作控制器的方法可以包括将从PN序列发生器提供的伪噪声（PN）序列存储在种子表的第i个区域中，并将PN序列从第i个区域循环移位到第（i + 1个） ）表中的区域形成表。 该表可能包括行和列区域。 用于操作控制器的方法可以包括从序列发生器接收序列，将序列分解成种子单元，将分离序列存储在种子表的第j个区域中，以及形成包括与分离序列相对应的种子单元的表 存储在第j个区域。 用于操作控制器的方法可以包括将从序列生成器提供的序列存储在包括多个区域的种子表中，并且将表中的序列循环移位，直到在每个区域中形成种子。

公开(公告)号：US08522124B2

公开(公告)日：2013-08-27

申请号：US13069834

申请日：2011-03-23

申请人： Yong-June Kim ,  Jun-Jin Kong ,  Young-Hwan Lee ,  Jae-Hong Kim

发明人： Yong-June Kim ,  Jun-Jin Kong ,  Young-Hwan Lee ,  Jae-Hong Kim

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： G06F11/1048

摘要： An error control coding (ECC) circuit includes a first decoder, a second decoder, and a controller. The first decoder receives encoded data comprising a first parity and a second parity. The first decoder decodes the encoded data to a first code by using the first parity. The second decoder is connected to the first decoder. The second decoder is configured to decode the encoded data when the first decoder is deactivated and decode the first code using the second parity when the first decoder is deactivated. The controller transmits a control signal to the first decoder and the second decoder to control the first decoder and the second decoder.

摘要翻译： 错误控制编码（ECC）电路包括第一解码器，第二解码器和控制器。 第一解码器接收包括第一奇偶校验和第二奇偶校验的编码数据。 第一解码器通过使用第一奇偶校验将编码数据解码为第一代码。 第二解码器连接到第一解码器。 第二解码器被配置为当第一解码器被去激活时解码编码数据，并且当第一解码器被去激活时使用第二奇偶校验解码第一代码。 控制器向第一解码器和第二解码器发送控制信号以控制第一解码器和第二解码器。

公开(公告)号：US20130198589A1

公开(公告)日：2013-08-01

申请号：US13612074

申请日：2012-09-12

申请人： Seong Hyeog CHOI ,  Jun Jin KONG ,  Hong Rak SON

发明人： Seong Hyeog CHOI ,  Jun Jin KONG ,  Hong Rak SON

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1072 ,  G06F11/108 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

摘要： According to example embodiments, a method of controlling a memory controller includes executing an error correction code (ECC) on first page data that has been read from a non-volatile memory device using a first read voltage level, estimating a second read voltage level for reading the first page data using metadata of second page data when an uncorrectable error is detected in the first page data according to a result of executing the ECC.

摘要翻译： 根据示例实施例，一种控制存储器控制器的方法包括：对使用第一读取电压电平从非易失性存储器件读取的第一页数据执行纠错码（ECC），估计第二读取电压电平 根据执行ECC的结果在第一页数据中检测到不可校正的错误时，使用第二页数据的元数据读取第一页数据。

公开(公告)号：US08499217B2

公开(公告)日：2013-07-30

申请号：US12153121

申请日：2008-05-14

申请人： Seung-Hwan Song ,  Jun Jin Kong ,  Jae Hong Kim ,  Kyoung Lae Cho ,  Sung Chung Park

发明人： Seung-Hwan Song ,  Jun Jin Kong ,  Jae Hong Kim ,  Kyoung Lae Cho ,  Sung Chung Park

IPC分类号： H03M13/00 ,  G06F11/00 ,  G11C29/00

CPC分类号： G06F11/141 ,  G06F11/1012 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/10 ,  G11C29/00

摘要： Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.

公开(公告)号：US20130132644A1

公开(公告)日：2013-05-23

申请号：US13615889

申请日：2012-09-14

申请人： Seong-Hyeog CHOI ,  Jun-jin KONG ,  Hong-Rak SON ,  Sang-Yong YOON

发明人： Seong-Hyeog CHOI ,  Jun-jin KONG ,  Hong-Rak SON ,  Sang-Yong YOON

IPC分类号： G06F12/00

CPC分类号： G06F12/0607 ,  G06F12/0246 ,  G06F2212/7203

摘要： A method of programming a nonvolatile memory device including a page buffer is provided. The method includes loading first page data and second page data into the page buffer; performing, by the page buffer, a first selective dump operation on the first page data and the second page data to generate first interleaved page data; performing, by the page buffer, a second selective dump operation on the first page data and the second page data to generate second interleaved page data; and programming the first interleaved page data and the second interleaved page data into a multi-level cell block.

摘要翻译： 提供了一种编程包括页面缓冲器的非易失性存储器件的方法。 该方法包括将第一页数据和第二页数据加载到页缓冲器中; 由所述页缓冲器执行对所述第一页数据和所述第二页数据的第一选择性转储操作，以产生第一交错页数据; 由页缓冲器对第一页数据和第二页数据执行第二选择性转储操作以产生第二交错页数据; 以及将所述第一交织页数据和所述第二交织页数据编程为多级单元块。

公开(公告)号：US08239747B2

公开(公告)日：2012-08-07

申请号：US12216744

申请日：2008-07-10

申请人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

发明人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

IPC分类号： G06F11/00

CPC分类号： G06F11/1072 ,  H03M13/09 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152

摘要： Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.

摘要翻译： 示例性实施例可以提供存储器件和存储器数据读取方法。 根据示例实施例的存储器件可以包括多位单元阵列，错误检测器，其可以从多位单元阵列中的存储器页读取第一数据页，并且可以检测第一数据页的错误位， 以及估计器，其可以识别存储错误位的多位单元，并且可以估计存储在所识别的多位单元中的数据在第二数据页的数据中。 因此，存储器件和存储器数据读取方法可以具有当读取存储在多位单元中的数据并且监视多位单元的状态而没有额外开销时减小误差的效果。

公开(公告)号：US08230157B2

公开(公告)日：2012-07-24

申请号：US12155647

申请日：2008-06-06

申请人： Jaehong Kim ,  Kyoung Lae Cho ,  Jun Jin Kong ,  Heeseok Eun ,  Seung-Hwan Song

发明人： Jaehong Kim ,  Kyoung Lae Cho ,  Jun Jin Kong ,  Heeseok Eun ,  Seung-Hwan Song

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F11/00 ,  G06F11/10 ,  H03M13/00 ,  G11C29/00

CPC分类号： G11C11/5628 ,  G11C11/5671 ,  G11C29/00

摘要： Memory devices and multi-bit programming methods are provided. A memory device may include a plurality of memory units; a data separator that separates data into a plurality of groups; a selector that rotates each of the plurality of groups and transmits each of the groups to at least one of the plurality of memory units. The plurality of memory units may include page buffers that may program the transmitted group in a plurality of multi-bit cell arrays using a different order of a page programming operation. Through this, evenly reliable data pages may be generated.

摘要翻译： 提供了存储器件和多位编程方法。 存储器件可以包括多个存储器单元; 数据分离器，将数据分离成多个组; 选择器，其使所述多个组中的每一个旋转，并将所述组中的每一个发送到所述多个存储器单元中的至少一个。 多个存储器单元可以包括可以使用页面编程操作的不同顺序对多个多位单元阵列中的发送组进行编程的页缓冲器。 通过此，可能会生成均匀可靠的数据页。