利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

71 条记录 (耗时 0.025 秒)

    METHOD OF ESTIMATING AND CORRECTING ERRORS IN MEMORY CELLS
    1.
    发明申请
    METHOD OF ESTIMATING AND CORRECTING ERRORS IN MEMORY CELLS 有权
    估计和校正记忆细胞中的错误的方法

    公开(公告)号：US20100115377A1

    公开(公告)日：2010-05-06

    申请号：US12607768

    申请日：2009-10-28

    申请人： Jaehong Kim ,  Yong June Kim ,  Seung Hwan Song

    发明人： Jaehong Kim ,  Yong June Kim ,  Seung Hwan Song

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/1108 ,  G06F11/1072

    摘要： A method, implemented by at least an error correction code (ECC) decoder and a controller, estimates and corrects errors in memory cells. The method includes identifying a first candidate group of memory cells having an error-generation possibility using a first method for error estimation; identifying a second candidate group of memory cells having an error-generation possibility using a second method for error estimation; and correcting errors in at least one cell commonly included in the first and second candidate groups.

    摘要翻译： 至少由纠错码（ECC）解码器和控制器实施的方法估计和校正存储器单元中的错误。 该方法包括使用第一种误差估计方法来识别具有错误产生可能性的存储器单元的第一候选组; 使用用于错误估计的第二方法识别具有错误生成可能性的第二候选组存储器单元; 以及校正通常包括在第一和第二候选组中的至少一个单元中的错误。

    Data Processing System Having ECC Encoding and Decoding Circuits Therein with Code Rate Selection Based on Bit Error Rate Detection
    3.
    发明申请
    Data Processing System Having ECC Encoding and Decoding Circuits Therein with Code Rate Selection Based on Bit Error Rate Detection 审中-公开
    具有基于误码率检测的码率选择的ECC编码和解码电路的数据处理系统

    公开(公告)号：US20100241928A1

    公开(公告)日：2010-09-23

    申请号：US12716793

    申请日：2010-03-03

    申请人： Jaehong Kim ,  Yong June Kim ,  Junjin Kong ,  Seung-Hwan Song

    发明人： Jaehong Kim ,  Yong June Kim ,  Junjin Kong ,  Seung-Hwan Song

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/618 ,  G06F11/1012 ,  H03M13/13 ,  H03M13/353 ,  H03M13/3738 ,  H03M13/6356 ,  H03M13/6362

    摘要： A data processing system includes an error checking and correction (ECC) encoding circuit, an integrated circuit memory and a code rate control circuit. The ECC encoding circuit is configured to selectively apply a plurality of unique ECC code rates to write data received by the data processing system during an operation to convert the write data into encoded data, in response to a code rate selection signal. The integrated circuit memory includes a plurality of storage regions therein. These storage regions are configured to receive respective portions of the encoded data from the ECC encoding circuit. The code rate control circuit is configured to generate the code rate selection signal. This code rate selection signal has a value that specifies the corresponding ECC code rate to be applied to respective portions of the write data.

    摘要翻译： 数据处理系统包括纠错（ECC）编码电路，集成电路存储器和码率控制电路。 ECC编码电路被配置为响应于码率选择信号，在操作期间选择性地应用多个唯一ECC码率来写入由数据处理系统接收的数据，以将写入数据转换为编码数据。 集成电路存储器包括多个存储区域。 这些存储区域被配置为从ECC编码电路接收编码数据的相应部分。 码率控制电路被配置为产生码率选择信号。 该码率选择信号具有指定应用于写入数据的各个部分的相应的ECC码率的值。

    Non-volatile memory device, memory card and system, and method determining read voltage by comparing referenced program data with comparative read data
    4.
    发明授权
    Non-volatile memory device, memory card and system, and method determining read voltage by comparing referenced program data with comparative read data 失效
    非易失性存储器件，存储卡和系统，以及通过将参考程序数据与比较读取数据进行比较来确定读取电压的方法

    公开(公告)号：US08773922B2

    公开(公告)日：2014-07-08

    申请号：US12614545

    申请日：2009-11-09

    申请人： Seung-Hwan Song ,  Jaehong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Jun Jin Kong ,  Jong Han Kim

    发明人： Seung-Hwan Song ,  Jaehong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Jun Jin Kong ,  Jong Han Kim

    IPC分类号： G11C7/06

    CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C29/00 ,  G11C2211/5634

    摘要： A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit.

    摘要翻译： 公开了一种非易失性半导体存储器件及确定读取电压的相关方法。 非易失性半导体存储器件包括： 包括多个存储单元的存储单元阵列，读电压确定单元，被配置为通过将在编程操作期间获得的参考数据与在随后的读取操作期间获得的比较数据进行比较来确定最佳读取电压，并将当前读取电压改变为新的 基于比较结果的读取电压和读取电压生成单元，被配置为响应于由读取电压确定单元提供的读取电压控制信号而产生新的读取电压。

    Method of estimating and correcting errors in memory cells
    5.
    发明授权
    Method of estimating and correcting errors in memory cells 有权
    估计和纠正存储单元错误的方法

    公开(公告)号：US08316279B2

    公开(公告)日：2012-11-20

    申请号：US12607768

    申请日：2009-10-28

    申请人： Jaehong Kim ,  Yong June Kim ,  Seung Hwan Song

    发明人： Jaehong Kim ,  Yong June Kim ,  Seung Hwan Song

    IPC分类号： G11C29/00

    CPC分类号： H03M13/1108 ,  G06F11/1072

    摘要： A method, implemented by at least an error correction code (ECC) decoder and a controller, estimates and corrects errors in memory cells. The method includes identifying a first candidate group of memory cells having an error-generation possibility using a first method for error estimation; identifying a second candidate group of memory cells having an error-generation possibility using a second method for error estimation; and correcting errors in at least one cell commonly included in the first and second candidate groups.

    摘要翻译： 至少由纠错码（ECC）解码器和控制器实施的方法估计并校正存储器单元中的错误。 该方法包括使用第一种误差估计方法来识别具有错误产生可能性的存储器单元的第一候选组; 使用用于错误估计的第二方法识别具有错误生成可能性的第二候选组存储器单元; 以及校正通常包括在第一和第二候选组中的至少一个单元中的错误。

    Memory devices and data decision methods
    7.
    发明授权
    Memory devices and data decision methods 有权
    内存设备和数据决策方法

    公开(公告)号：US08200607B2

    公开(公告)日：2012-06-12

    申请号：US12292539

    申请日：2008-11-20

    申请人： Jae Hong Kim ,  Heeseok Eun ,  Yong June Kim ,  Jun Jin Kong ,  Seung-Hwan Song

    发明人： Jae Hong Kim ,  Heeseok Eun ,  Yong June Kim ,  Jun Jin Kong ,  Seung-Hwan Song

    IPC分类号： G06F17/00 ,  G06N5/02

    CPC分类号： G06N99/005

    摘要： Disclosed are a memory device and a data decision method. The memory device may include a memory cell array, and a decision unit configured to read first data from the memory cell array via a first channel, perform at least one of a hard and soft decision on the first data using a first number of decision levels set based on characteristics of the first channel, read second data from the memory cell array via a second channel, and perform a soft decision on the second data using a second number of decision levels set based on characteristics of the second channel.

    摘要翻译： 公开了一种存储器件和数据判定方法。 存储器装置可以包括存储单元阵列，以及判定单元，被配置为经由第一通道从存储单元阵列读取第一数据，使用第一数量的判定级别对第一数据执行硬判决和软判决中的至少一个 基于第一信道的特性设置，经由第二信道从存储器单元阵列读取第二数据，并且使用基于第二信道的特性设置的第二数量的判定级来对第二数据执行软判决。

    Memory device and memory programming method
    8.
    发明授权
    Memory device and memory programming method 有权
    存储器和存储器编程方法

    公开(公告)号：US07864574B2

    公开(公告)日：2011-01-04

    申请号：US12453108

    申请日：2009-04-29

    申请人： Kyoung Lae Cho ,  Yong June Kim ,  Seung-Hwan Song ,  Jun Jin Kong

    发明人： Kyoung Lae Cho ,  Yong June Kim ,  Seung-Hwan Song ,  Jun Jin Kong

    IPC分类号： G11C11/34

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

    摘要： Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page.

    摘要翻译： 提供的是存储器件和存储器编程方法。 存储器件可以包括包括多个多位单元的多位单元阵列，编程单元，被配置为对多个多位单元中的第一数据页进行编程，并编程多位单元中的第二数据页 具有编程的第一数据页的单元，被配置为将多位单元与编程的第一数据页划分为第一组和第二组的第一控制器，以及配置成将每个的第一数据页的目标阈值电压间隔 基于第一读取电压电平和第二数据页面包括在第一组中的多位单元，并且基于第二读取阈值电压电平来设置包括在第二组中的每个多位单元的目标阈值电压间隔，以及 第二个数据页面。

    Memory device and memory programming method
    9.
    发明申请
    Memory device and memory programming method 有权
    存储器和存储器编程方法

    公开(公告)号：US20090285023A1

    公开(公告)日：2009-11-19

    申请号：US12453108

    申请日：2009-04-29

    申请人： Kyoung Lae Cho ,  Yong June Kim ,  Seung-Hwan Song ,  Jun Jin Kong

    发明人： Kyoung Lae Cho ,  Yong June Kim ,  Seung-Hwan Song ,  Jun Jin Kong

    IPC分类号： G11C16/02 ,  G11C7/00 ,  G11C16/06

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

    摘要： Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page.

    摘要翻译： 提供的是存储器件和存储器编程方法。 存储器件可以包括包括多个多位单元的多位单元阵列，编程单元，被配置为对多个多位单元中的第一数据页进行编程，并编程多位单元中的第二数据页 具有编程的第一数据页的单元，被配置为将多位单元与编程的第一数据页划分为第一组和第二组的第一控制器，以及配置成将每个的第一数据页的目标阈值电压间隔 基于第一读取电压电平和第二数据页面包括在第一组中的多位单元，并且基于第二读取阈值电压电平来设置包括在第二组中的每个多位单元的目标阈值电压间隔，以及 第二个数据页面。

    Memory devices and data decision methods
    10.
    发明申请
    Memory devices and data decision methods 有权
    内存设备和数据决策方法

    公开(公告)号：US20090234792A1

    公开(公告)日：2009-09-17

    申请号：US12292539

    申请日：2008-11-20

    申请人： Jae Hong Kim ,  Heeseok Eun ,  Yong June Kim ,  Jun Jin Kong ,  Seung-Hwan Song

    发明人： Jae Hong Kim ,  Heeseok Eun ,  Yong June Kim ,  Jun Jin Kong ,  Seung-Hwan Song

    IPC分类号： G06N5/00

    CPC分类号： G06N99/005

    摘要： Disclosed are a memory device and a data decision method. The memory device may include a memory cell array, and a decision unit configured to read first data from the memory cell array via a first channel, perform at least one of a hard and soft decision on the first data using a first number of decision levels set based on characteristics of the first channel, read second data from the memory cell array via a second channel, and perform a soft decision on the second data using a second number of decision levels set based on characteristics of the second channel.

    摘要翻译： 公开了一种存储器件和数据判定方法。 存储器装置可以包括存储单元阵列，以及判定单元，被配置为经由第一通道从存储单元阵列读取第一数据，使用第一数量的判定级别对第一数据执行硬判决和软判决中的至少一个 基于第一信道的特性设置，经由第二信道从存储器单元阵列读取第二数据，并且使用基于第二信道的特性设置的第二数量的判定级来对第二数据执行软判决。