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    Data processing systems and methods providing error correction
    2.
    发明授权
    Data processing systems and methods providing error correction 有权
    提供纠错的数据处理系统和方法

    公开(公告)号：US09100054B2

    公开(公告)日：2015-08-04

    申请号：US13414002

    申请日：2012-03-07

    申请人： Kijun Lee ,  Junjin Kong ,  Sejin Lim ,  Jaehong Kim ,  Hong-Rak Son ,  Yong-June Kim

    发明人： Kijun Lee ,  Junjin Kong ,  Sejin Lim ,  Jaehong Kim ,  Hong-Rak Son ,  Yong-June Kim

    IPC分类号： H03M13/29 ,  H03M13/37 ,  H03M13/33 ,  H03M13/09 ,  H03M13/11 ,  H03M13/15

    CPC分类号： H03M13/2906 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2933 ,  H03M13/2957 ,  H03M13/3738

    摘要： A method may be provided to detect and correct data errors in a data system where a data message has been encoded with outer parity bits based on the data message using an outer encoding technique to provide an outer codeword and with inner parity bits based on the outer codeword using an inner encoding technique different than the outer encoding technique to provide an inner codeword. The method may include using the inner parity bits and an inner decoding technique corresponding to the inner encoding technique to perform inner decoding of the inner codeword. Responsive to performing inner decoding of the inner codeword without error, the data message may be extracted from a result of inner decoding the inner codeword without using the outer parity bits to decode the result of inner decoding the inner codeword. Related systems are also discussed.

    摘要翻译： 可以提供一种方法来检测和校正数据系统中的数据错误，其中数据消息已经使用外部奇偶校验比特基于数据消息使用外部编码技术进行编码，以提供外部码字，并且具有基于外部奇偶校验位的内部奇偶校验位 码字使用与外部编码技术不同的内部编码技术来提供内部码字。 该方法可以包括使用内部奇偶校验位和对应于内部编码技术的内部解码技术来执行内部码字的内部解码。 响应于无误地执行内部码字的内部解码，可以从内部码字的内部解码的结果中提取数据消息，而不使用外部奇偶校验位来解码内​​部码字的内部解码结果。 还讨论了相关系统。

    Memory systems and defective block management methods related thereto
    3.
    发明授权
    Memory systems and defective block management methods related thereto 有权
    与其相关的存储器系统和有缺陷的块管理方法

    公开(公告)号：US08417988B2

    公开(公告)日：2013-04-09

    申请号：US12784683

    申请日：2010-05-21

    申请人： Yong-June Kim ,  Junjin Kong ,  Jaehong Kim ,  Han Woong Yoo

    发明人： Yong-June Kim ,  Junjin Kong ,  Jaehong Kim ,  Han Woong Yoo

    IPC分类号： G06F11/26 ,  G06F11/00

    CPC分类号： G11C29/82

    摘要： Memory systems and related defective block management methods are provided. Methods for managing a defective block in a memory device include allocating a defective block when a memory block satisfies a defective block condition. The allocated defective block is cancelled when the allocated defective block satisfies a defective block cancellation condition.

    摘要翻译： 提供了存储器系统和相关的有缺陷的块管理方法。 用于管理存储器件中的缺陷块的方法包括当存储器块满足缺陷块状态时分配缺陷块。 当分配的缺陷块满足缺陷块取消条件时，分配的缺陷块被取消。

    NONVOLATILE MEMORY DEVICE AND METHOD SYSTEM INCLUDING THE SAME
    5.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD SYSTEM INCLUDING THE SAME 审中-公开
    非易失性存储器件和包括其的方法系统

    公开(公告)号：US20100238705A1

    公开(公告)日：2010-09-23

    申请号：US12698720

    申请日：2010-02-02

    申请人： Yong June Kim ,  Jaehong Kim ,  Junjin Kong

    发明人： Yong June Kim ,  Jaehong Kim ,  Junjin Kong

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C7/1006 ,  G11C7/1042 ,  G11C8/10 ,  G11C11/5628 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2211/5623

    摘要： A nonvolatile memory device performs interleaving of data to be stored in each wordline (memory page), or of data to be stored in multiple wordlines (memory pages). The NVM includes a memory cell array, a storage circuit of a de-interleaving circuit, and a read/write circuit. The storage circuit of the de-interleaving circuit is configured to store program data to be written interleaved into the memory cell array. The read/write circuit is configured to control the interleaved/deinterleaved data input/output between the memory cell array and the storage circuit. The write operation unit size may be the same or different from the read operation unit size. The storage circuit stores the program data of integer k times of a common divisor of a read operation unit size and a write operation unit size of the read/write circuit, wherein k may equal ‘m’ (the number of bits stored in each memory cell of the NVM).

    摘要翻译： 非易失性存储器件执行要存储在每个字线（存储器页）中的数据或要存储在多个字线（存储器页）中的数据的交织。 NVM包括存储单元阵列，解交织电路的存储电路和读/写电路。 解交织电路的存储电路被配置为将要被交织的程序数据存储到存储单元阵列中。 读/写电路被配置为控制存储单元阵列和存储电路之间的交错/去交织的数据输入/输出。 写入操作单元尺寸可以与读取操作单元尺寸相同或不同。 存储电路存储读/写电路的读操作单元大小和写操作单元大小的公约数的整数k倍的程序数据，其中k可以等于“m”（存储在每个存储器中的位数 NVM的单元）。

    Semiconductor memory device and data processing method thereof
    7.
    发明授权
    Semiconductor memory device and data processing method thereof 有权
    半导体存储器件及其数据处理方法

    公开(公告)号：US08806302B2

    公开(公告)日：2014-08-12

    申请号：US12654578

    申请日：2009-12-23

    申请人： Yong June Kim ,  Junjin Kong ,  Jaehong Kim ,  Hong Rak Son

    发明人： Yong June Kim ,  Junjin Kong ,  Jaehong Kim ,  Hong Rak Son

    IPC分类号： G11C29/00

    CPC分类号： G11C13/00 ,  G11C7/1006 ,  G11C11/5628 ,  G11C13/0033 ,  G11C16/3427 ,  G11C29/00

    摘要： Provided is a data processing method in a semiconductor memory device. The data processing method arranges data, which is to be programmed in a row and column of a nonvolatile memory device, in a row or column direction. The data processing method encodes the programmed data into a modulation code in the row or column direction such that adjacent pairs of memory cells of the nonvolatile memory device are prevented from being programmed into first and second states.

    摘要翻译： 提供了一种半导体存储器件中的数据处理方法。 数据处理方法按行或列方向排列要编程在非易失性存储器件的行和列中的数据。 数据处理方法将编程数据编码成行或列方向的调制码，使得非易失性存储器件的相邻存储单元对被阻止被编程到第一和第二状态。

    Multi-bit cell memory devices using error correction coding and methods of operating the same
    8.
    发明授权
    Multi-bit cell memory devices using error correction coding and methods of operating the same 有权
    使用纠错编码的多位单元存储器件及其操作方法

    公开(公告)号：US08482977B2

    公开(公告)日：2013-07-09

    申请号：US13039004

    申请日：2011-03-02

    申请人： Yong June Kim ,  Jaehong Kim ,  Junjin Kong ,  Hong Rak Son

    发明人： Yong June Kim ,  Jaehong Kim ,  Junjin Kong ,  Hong Rak Son

    IPC分类号： G11C16/04

    CPC分类号： G11C16/04

    摘要： A memory device includes a plurality of multi-bit memory cells. A plurality of input data bits are encoded according to an error correction code to generate a codeword including a plurality of groups of bits. Respective ones of the plurality of multi-bit memory cells are programmed to represent respective ones of the groups of bits of the codeword. The groups of bits of the codeword may be groups of consecutive bits. In some embodiments, the multi-bit memory cells are each configured to store in bits and a length of the codeword is an integer multiple of m. Data may be read from the multi-bit memory cells in page units or cell units to recover the codeword, and the recovered code word may be decode according to the error correction code to recover the input data bits.

    摘要翻译： 存储器件包括多个多位存储器单元。 根据纠错码对多个输入数据位进行编码，以产生包括多个位组的码字。 多个多位存储器单元中的相应的多位存储器单元被编程为表示码字的位组中的相应的一组。 码字的比特组可以是连续比特的组。 在一些实施例中，多位存储器单元被配置为以比特存储，并且码字的长度是m的整数倍。 可以从页单元或单元单元中的多位存储单元读取数据以恢复码字，并且可以根据纠错码对恢复的码字进行解码以恢复输入数据位。

    Memory Systems and Defective Block Management Methods Related Thereto
    9.
    发明申请
    Memory Systems and Defective Block Management Methods Related Thereto 有权
    与其相关的内存系统和缺陷块管理方法

    公开(公告)号：US20100306583A1

    公开(公告)日：2010-12-02

    申请号：US12784683

    申请日：2010-05-21

    申请人： Yong-June Kim ,  Junjin Kong ,  Jaehong Kim ,  Han Woong Yoo

    发明人： Yong-June Kim ,  Junjin Kong ,  Jaehong Kim ,  Han Woong Yoo

    IPC分类号： G06F11/20

    CPC分类号： G11C29/82

    摘要： Memory systems and related defective block management methods are provided. Methods for managing a defective block in a memory device include allocating a defective block when a memory block satisfies a defective block condition. The allocated defective block is cancelled when the allocated defective block satisfies a defective block cancellation condition.

    摘要翻译： 提供了存储器系统和相关的有缺陷的块管理方法。 用于管理存储器件中的缺陷块的方法包括当存储器块满足缺陷块状态时分配缺陷块。 当分配的缺陷块满足缺陷块取消条件时，分配的缺陷块被取消。

    Data Processing System Having ECC Encoding and Decoding Circuits Therein with Code Rate Selection Based on Bit Error Rate Detection
    10.
    发明申请
    Data Processing System Having ECC Encoding and Decoding Circuits Therein with Code Rate Selection Based on Bit Error Rate Detection 审中-公开
    具有基于误码率检测的码率选择的ECC编码和解码电路的数据处理系统

    公开(公告)号：US20100241928A1

    公开(公告)日：2010-09-23

    申请号：US12716793

    申请日：2010-03-03

    申请人： Jaehong Kim ,  Yong June Kim ,  Junjin Kong ,  Seung-Hwan Song

    发明人： Jaehong Kim ,  Yong June Kim ,  Junjin Kong ,  Seung-Hwan Song

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/618 ,  G06F11/1012 ,  H03M13/13 ,  H03M13/353 ,  H03M13/3738 ,  H03M13/6356 ,  H03M13/6362

    摘要： A data processing system includes an error checking and correction (ECC) encoding circuit, an integrated circuit memory and a code rate control circuit. The ECC encoding circuit is configured to selectively apply a plurality of unique ECC code rates to write data received by the data processing system during an operation to convert the write data into encoded data, in response to a code rate selection signal. The integrated circuit memory includes a plurality of storage regions therein. These storage regions are configured to receive respective portions of the encoded data from the ECC encoding circuit. The code rate control circuit is configured to generate the code rate selection signal. This code rate selection signal has a value that specifies the corresponding ECC code rate to be applied to respective portions of the write data.

    摘要翻译： 数据处理系统包括纠错（ECC）编码电路，集成电路存储器和码率控制电路。 ECC编码电路被配置为响应于码率选择信号，在操作期间选择性地应用多个唯一ECC码率来写入由数据处理系统接收的数据，以将写入数据转换为编码数据。 集成电路存储器包括多个存储区域。 这些存储区域被配置为从ECC编码电路接收编码数据的相应部分。 码率控制电路被配置为产生码率选择信号。 该码率选择信号具有指定应用于写入数据的各个部分的相应的ECC码率的值。