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公开(公告)号：US11573853B2
公开(公告)日：2023-02-07
申请号：US17218535
申请日：2021-03-31
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Vilas Sridharan , Sudhanva Gurumurthi
Abstract: Error checking data used in offloaded operations is disclosed. A remote execution device receives a request from a host to store a data block in a memory region. The data block includes data and host-generated error checking information for the data. The remote execution device updates the data block by overwriting the host-generated error checking information with locally generated error checking information for the data. The data block is then stored in the memory region.
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公开(公告)号：US20230004459A1
公开(公告)日：2023-01-05
申请号：US17864804
申请日：2022-07-14
Applicant: Advanced Micro Devices, Inc.
Inventor： James R. Magro , Kedarnath Balakrishnan , Vilas Sridharan
Abstract: A memory controller includes a memory channel controller adapted to receive memory access requests and dispatch associated commands addressable in a system memory address space to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.
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公开(公告)号：US20220156167A1
公开(公告)日：2022-05-19
申请号：US17588779
申请日：2022-01-31
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov , Michael Ignatowski , Vilas Sridharan
IPC: G06F11/20
Abstract: A method includes, in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in a remapping table the faulted segment with a patch segment in a patch memory region, and in response to receiving from a processor a memory access request directed to the faulted segment, servicing the memory access request from the patch segment by performing the requested memory access at the patch segment based on a patch segment address identifying the location of the patch segment. The patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.
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公开(公告)号：US20220091921A1
公开(公告)日：2022-03-24
申请号：US17544074
申请日：2021-12-07
Applicant: Advanced Micro Devices, Inc.
Inventor： Kedarnath Balakrishnan , James R. Magro , Kevin Michael Lepak , Vilas Sridharan
Abstract: A data processor includes provides memory commands to a memory channel according to predetermined criteria. The data processor includes a first error code generation circuit, a second error code generation circuit, and a queue. The first error code generation circuit generates a first type of error code in response to data of a write request. The second error code generation circuit generates a second type of error code for the write request, the second type of error code different from the first type of error code. The queue is coupled to the first error code generation circuit and to the second error code generation circuit, for provides write commands to an interface, the write commands including the data, the first type of error code, and the second type of error code.
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Patent Agency Ranking
公开(公告)号：US11200106B2
公开(公告)日：2021-12-14
申请号：US16705913
申请日：2019-12-06
Applicant: Advanced Micro Devices, Inc.
Inventor： Kedarnath Balakrishnan , James R. Magro , Kevin Michael Lepak , Vilas Sridharan
Abstract: A data processing system includes a memory channel, a memory coupled to the memory channel, and a data processor. The data processor is coupled to the memory channel and accesses the memory over the memory channel using a packet structure defining a plurality of commands and having corresponding address bits, data bits, and user bits. The data processor communicates with the memory over the memory channel using a first type of error code. In response to a write access request, the data processor calculates a different, second type of error code and appends each bit of the second type of error code as a corresponding one of the user bits. The memory stores the user bits in the memory in response to a write command, and transfers the user bits to the data processor in a read response packet in response to a read command.
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公开(公告)号：US20210200618A1
公开(公告)日：2021-07-01
申请号：US16730113
申请日：2019-12-30
Applicant: Advanced Micro Devices, Inc.
Inventor： James R. Magro , Kedarnath Balakrishnan , Vilas Sridharan
Abstract: A memory controller includes a command queue, a memory interface queue, and a non-volatile error reporting circuit. The command queue receives memory access commands including volatile reads, volatile writes, non-volatile reads, and non-volatile writes, and an output. The memory interface queue has an input coupled to the output of the command queue, and an output for coupling to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.
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公开(公告)号：US10684902B2
公开(公告)日：2020-06-16
申请号：US15662524
申请日：2017-07-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Vilas Sridharan , David A. Roberts
Abstract: Described herein are a method and apparatus for memory vulnerability prediction. A memory vulnerability predictor predicts the reliability of a memory region when it is first accessed, based on past program history. The memory vulnerability predictor uses a table to store reliability predictions and predicts reliability needs of a new memory region. A memory management module uses the reliability information to make decisions, (such as to guide memory placement policies in a heterogeneous memory system).
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公开(公告)号：US20140368513A1
公开(公告)日：2014-12-18
申请号：US13920574
申请日：2013-06-18
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Lyashevsky , Sudhanva Gurumurthi , Vilas Sridharan
IPC: G06T1/20
CPC classification number: G06F11/00 , G06F9/3851 , G06F9/52 , G06F11/1608 , G06F11/1633 , G06F11/1637 , G06F11/1654 , G06F11/1687 , G06F11/202 , G06F11/2038 , G06F11/2041 , G06F11/2048 , G06F2201/825 , G06F2201/83
Abstract: A system, method and computer program product to execute a first and a second work-item, and compare the signature variable of the first work-item to the signature variable of the second work-item. The first and the second work-items are mapped to an identifier via software. This mapping ensures that the first and second work-items execute exactly the same data for exactly the same code without changes to the underlying hardware. By executing the first and second work-items independently, the underlying computation of the first and second work-item can be verified. Moreover, system performance is not substantially affected because the execution results of the first and second work-items are compared only at specified comparison points.
Abstract translation: 一种用于执行第一和第二工作项目的系统，方法和计算机程序产品，并且将第一工作项目的签名变量与第二工作项目的签名变量进行比较。 第一个和第二个工作项通过软件映射到一个标识符。 此映射确保第一个和第二个工作项完全相同的数据完全相同的代码，而不会更改底层硬件。 通过独立地执行第一和第二工作项目，可以验证第一和第二工件的基础计算。 此外，系统性能基本上不受影响，因为第一和第二工作项目的执行结果仅在指定的比较点进行比较。
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49.发明申请公开(公告)号：US20140331207A1
公开(公告)日：2014-11-06
申请号：US14266131
申请日：2014-04-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Vilas Sridharan , Mark E. Wilkening , Sudhanva Gurumurthi
IPC: G06F11/36
CPC classification number: G06F11/3672 , G06F9/4843 , G06F11/34 , G06F11/3419 , G06F11/3471 , G06F11/3612
Abstract: The described embodiments include a program code testing system that determines the vulnerability of multi-threaded program code to soft errors. For multi-threaded program code, two to more threads from the program code may access shared architectural structures while the program code is being executed. The program code testing system determines accesses of architectural structures made by the two or more threads of the multi-threaded program code and uses the determined accesses to determine a time for which the program code is exposed to soft errors. From this time, the program code testing system determines a vulnerability of the program code to soft errors.
Abstract translation: 所描述的实施例包括程序代码测试系统，其确定多线程程序代码对软错误的脆弱性。 对于多线程程序代码，程序代码中的两个到更多的线程可以在执行程序代码时访问共享架构结构。 程序代码测试系统确定由多线程程序代码的两个或多个线程进行的架构结构的访问，并使用所确定的访问来确定程序代码暴露于软错误的时间。 从这时起，程序代码测试系统将程序代码的漏洞确定为软错误。
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