公开(公告)号：US11587930B2

公开(公告)日：2023-02-21

申请号：US17159534

申请日：2021-01-27

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Nitin K. Ingle ,  Sung-Kwan Kang

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

公开(公告)号：US20230040627A1

公开(公告)日：2023-02-09

申请号：US17879097

申请日：2022-08-02

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Sung-Kwan Kang

IPC: H01L27/11524 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Described is a semiconductor memory device and methods of manufacture. The semiconductor memory device comprises a memory array comprising at least one select-gate-for-drain (SGD) transistor and at least one memory transistor, the memory array having at least one strapping region and at least one strapping contact, the strapping contact connecting a select-gate-for-drain (SGD) transistor to a strapping line.

公开(公告)号：US20210399011A1

公开(公告)日：2021-12-23

申请号：US17346910

申请日：2021-06-14

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Mihaela A. Balseanu

IPC: H01L27/11582 ,  H01L29/423 ,  H01L21/28 ,  H01L21/67 ,  H01L21/687

Abstract: Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.

公开(公告)号：US11189635B2

公开(公告)日：2021-11-30

申请号：US16833899

申请日：2020-03-30

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Mukund Srinivasan ,  Sanjay Natarajan

IPC: H01L27/11582 ,  H01L29/792 ,  H01L27/11575 ,  H01L21/3205 ,  H01L21/311 ,  H01L21/677 ,  H01L21/02 ,  H01L21/3213

Abstract: Methods of manufacturing memory devices are provided. The methods decrease the thickness of the first layers and increase the thickness of the second layers. Semiconductor devices are described having a film stack comprising alternating nitride and second layers in a first portion of the device, the alternating nitride and second layers of the film stack having a nitride:oxide thickness ratio (Nf:Of); and a memory stack comprising alternating word line and second layers in a second portion of the device, the alternating word line and second layers of the memory stack having a word line:oxide thickness ratio (Wm:Om), wherein 0.1(Wm:Om)

公开(公告)号：US20210233779A1

公开(公告)日：2021-07-29

申请号：US17147578

申请日：2021-01-13

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Sung-Kwan Kang

IPC: H01L21/321 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11582

Abstract: Memory devices and methods of manufacturing memory devices are provided. The device and methods described suppress oxidation of metal layers exposed to ambient oxygen. After an opening is formed, a nitridation process occurs to nitridate the surface of the exposed metal layer inside the opening. The nitridated region formed on the surface of metal layer inside the opening works as a barrier layer for oxygen diffusion. In addition, the nitridated region works as an electrode for charge trap memory cells.

公开(公告)号：US20200251151A1

公开(公告)日：2020-08-06

申请号：US16779830

申请日：2020-02-03

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Sanjay Natarajan ,  Sung-Kwan Kang ,  Lequn Liu

IPC: G11C5/06 ,  H01L27/108

Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.