公开(公告)号：US20080313389A1

公开(公告)日：2008-12-18

申请号：US11929799

申请日：2007-10-30

申请人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

公开(公告)号：US20080235939A1

公开(公告)日：2008-10-02

申请号：US12033851

申请日：2008-02-19

申请人： Siew S. Hiew ,  Charles C. Lee ,  Paul Hsueh ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： Siew S. Hiew ,  Charles C. Lee ,  Paul Hsueh ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： H05K3/20 ,  G11C11/34

CPC分类号： H05K3/284 ,  H01L21/561 ,  H01L24/97 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/1815 ,  H05K1/117 ,  H05K3/0032 ,  H05K3/0052 ,  H05K2201/09154 ,  H05K2201/10159 ,  H05K2203/0228 ,  H05K2203/0746 ,  H05K2203/1316 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49171 ,  Y10T29/49789 ,  Y10T29/49798 ,  H01L2224/85 ,  H01L2924/00

摘要： A method for fabricating MicroSD devices includes forming a PCB panel having multiple PCB regions arranged in parallel rows. Passive components are attached by conventional surface mount technology (SMT) techniques. IC chips, including a MicroSD controller chip and a flash memory chip, are attached to the PCB by wire bonding or other chip-on-board (COB) technique. A molded layer is then formed over the IC chips and passive components using a mold that prevents formation of plastic on the upper surface of each PCB. The panel is then singulated using one of a laser cutting method, an abrasive water jet cutting method, and a mechanical grinding method such that the resulting PCB substrate and plastic housing have the width, height and length specified by MicroSD specifications. A front edge chamfer process is then performed.

摘要翻译： 一种用于制造MicroSD器件的方法包括形成具有平行排布置的多个PCB区域的PCB面板。 无源元件通过常规表面贴装技术（SMT）技术连接。 包括MicroSD控制器芯片和闪存芯片在内的IC芯片通过引线接合或其他芯片上的（COB）芯片技术连接到PCB。 然后使用防止在每个PCB的上表面上形成塑料的模具在IC芯片和无源部件上形成模制层。 然后使用激光切割方法，磨料水射流切割方法和机械研磨方法之一将面板切片，使得所得PCB基板和塑料外壳具有由MicroSD规格规定的宽度，高度和长度。 然后执行前沿倒角处理。

公开(公告)号：US20080071978A1

公开(公告)日：2008-03-20

申请号：US11929847

申请日：2007-10-30

申请人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  Frank I. Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

摘要翻译： 电子数据闪存卡可由主机访问，并且包括连接到存储数据文件的闪存设备的处理单元，以及被激活以便与主计算机建立通信的输入 - 输出接口电路。 在一个实施例中，电子数据闪存卡使用USB输入/输出接口电路与主计算机进行通信。 闪速存储器控制器包括用于将由主计算机发送的逻辑地址转换成与闪存器件的扇区相关联的物理地址的索引。 该索引由参考来自各种查找表中的值和存储在闪存设备中的有效数据的仲裁逻辑控制。 闪存控制器还包括先进先出单元（FIFO），用于在后台进程中回收闪速存储器件的过时扇区，使得它们可用于重新编程。

公开(公告)号：US08180931B2

公开(公告)日：2012-05-15

申请号：US12651334

申请日：2009-12-31

申请人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma

发明人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F3/0661 ,  G06F3/0613 ,  G06F3/0688 ,  G11C11/5678 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30

摘要： An electronic flash-memory card has additional pipes for commands and status messages so that data pipes are not clogged with commands and status messages, allowing for a higher data throughput. The command and status pipes are activated when a UAS/BOT detector detects that a host is using a USB-Attached-SCSI (UAS) mode rather than a Bulk-Only-Transfer (BOT) mode. The host can send additional commands and data without waiting for completion of a prior command when operating in UAS mode but not while operating in BOT mode. A command queue (CQ) in the device re-orders commands for accessing flash memory and merges data in a RAM buffer. Smaller 1 KB USB packets in the data pipes are merged into larger 8 KB payloads in the RAM buffer, allowing for more efficient flash access.

摘要翻译： 电子闪存卡具有用于命令和状态消息的附加管道，使得数据管道不被命令和状态消息阻塞，从而允许更高的数据吞吐量。 当UAS / BOT检测器检测到主机正在使用USB-Attached-SCSI（UAS）模式而不是Bulk-Only-Transfer（BOT）模式时，命令和状态管道将被激活。 主机可以发送附加的命令和数据，而不必在UAS模式下操作时等待先前的命令完成，而不能在BOT模式下运行。 设备中的命令队列（CQ）重新命令用于访问闪存的命令，并将数据合并到RAM缓冲区中。 数据管道中较小的1 KB USB数据包被合并到RAM缓冲区中的较大的8 KB有效载荷中，从而实现更高效的闪存访问。

公开(公告)号：US08171204B2

公开(公告)日：2012-05-01

申请号：US12115128

申请日：2008-05-05

申请人： David Q. Chow ,  Frank Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： David Q. Chow ,  Frank Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F13/00

CPC分类号： G06F12/1416 ,  G06F3/0664 ,  G06F12/0851 ,  G06F12/0866 ,  G06F12/0897 ,  G06F21/32 ,  G06F21/78 ,  G06F21/79 ,  G06F2212/2022 ,  Y02D10/13

摘要： A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.

摘要翻译： 闪存系统存储由逻辑块地址（LBA）寻址的非易失性存储器件（NVMD）中的数据块。 NVBA将对LBA进行重新配置以进行磨损均衡和坏块重定位。 NVMD在由NVMD控制器访问的通道中进行交织。 NVMD控制器具有缓存存储在该通道中的NVMD中的块的控制器高速缓存，而NVMD还包含高速缓存。 多级缓存可以减少访问延迟。 电源由NVMD控制器中的电源控制器以多级管理，为NVMD内的电源管理器设置电源策略。 闪存系统中的多个NVMD控制器可以各自控制多个NVMD通道。 具有NVMD的闪存系统可能包括用于安全性的指纹读取器。

公开(公告)号：US08112574B2

公开(公告)日：2012-02-07

申请号：US12347306

申请日：2008-12-31

申请人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma

发明人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma

IPC分类号： G06F12/10

CPC分类号： G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C16/102 ,  G11C2216/30

摘要： A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N−1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables.

摘要翻译： 闪存控制器具有访问多电平单元（MLC）闪存的物理块的闪存接口。 扩展通用串行总线（EUSB）接口将主机命令加载到命令队列中，其中写入被重新排序并组合以减少闪存写入。 RAM中的部分逻辑到物理L2P映射表仅具有N组L2P映射表中的1个的条目。 其他N-1组存储在闪存中，并在发生L2P表错误时被提取到RAM中。 映射所需的RAM大大降低。 数据缓冲器存储一页主机写入数据。 扇区写入使用数据缓冲区进行合并。 当写入不同的页面时，数据缓冲区被刷新闪存，而当L2P表错过发生时，部分逻辑到物理映射表被刷新为闪存，当主机地址是N组的L2P中的不同的一个 映射表。

公开(公告)号：US07966462B2

公开(公告)日：2011-06-21

申请号：US11871627

申请日：2007-10-12

申请人： Charles C. Lee ,  Frank Yu ,  Ming-Shiang Shen ,  Abraham C. Ma ,  David Q. Chow

发明人： Charles C. Lee ,  Frank Yu ,  Ming-Shiang Shen ,  Abraham C. Ma ,  David Q. Chow

IPC分类号： G06F12/02

CPC分类号： G06F12/0607 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C16/0408 ,  G11C2211/5649

摘要： A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.

摘要翻译： 使用由物理顺序地址计数器生成的平面，块和页面地址从闪存中恢复RAM映射表。 RAM映射表在使用从逻辑块索引的最低位提取的交错比特的物理顺序地址计数器产生的平面交织序列之后恢复。 这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。 物理顺序地址计数器通过在中间物理块位之前递增平面交织比特，然后将MSB重定位到中间物理块比特之上来生成物理块号。 这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 还执行后台回收和ECC写入。

公开(公告)号：US07761653B2

公开(公告)日：2010-07-20

申请号：US11875648

申请日：2007-10-19

申请人： Charles C. Lee ,  David Q. Chow ,  Abraham C. Ma ,  Frank Yu ,  Ming-Shiang Shen

发明人： Charles C. Lee ,  David Q. Chow ,  Abraham C. Ma ,  Frank Yu ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F9/441

摘要： A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The boot code includes an initial boot loader, boot code and a control program that are executed by the flash microcontroller, and an operating system OS image and an external-host control program that are executed by an external host. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A first-reset-read address from the external host is captured by the microcontroller during its boot sequence and stored in a mapping table along with a physical address of the block in the SRAM buffer with the operating system OS image and the external-host control program. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory.

摘要翻译： 闪存微控制器具有静态随机存取存储器（SRAM）缓冲器，其存储从闪存读取的几个引导代码块。 引导代码包括由闪存微控制器执行的初始引导加载程序，引导代码和控制程序，以及由外部主机执行的操作系统OS映像和外部主机控制程序。 外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。 微控制器在其引导序列期间捕获来自外部主机的第一复位读取地址，并将其与SRAM缓冲器中具有操作系统OS映像和外部主机控制的块的物理地址一起存储在映射表中 程序。 引导加载器状态机读取闪存ID，并使用Flash存储器的时序参数对闪存参数寄存器进行编程。

公开(公告)号：US07690030B1

公开(公告)日：2010-03-30

申请号：US11458987

申请日：2006-07-20

申请人： Abraham C. Ma ,  Sun-Teck See ,  Charles C. Lee ,  Edward W. Lee ,  Ming-Shiang Shen

发明人： Abraham C. Ma ,  Sun-Teck See ,  Charles C. Lee ,  Edward W. Lee ,  Ming-Shiang Shen

IPC分类号： G06F7/04

CPC分类号： G06F12/1416 ,  G06F21/32 ,  G06F21/34 ,  G06F21/78 ,  G06K19/07 ,  G06K19/07354

摘要： An electronic data flash card with fingerprint capability is accessible by an host computer, and includes a processing unit connected to a flash memory device that stores a data file and reference fingerprint data of a person authorized to access the data file, a fingerprint sensor for scanning the fingerprint of a user and for generating input fingerprint data that can be compared with the stored reference fingerprint data, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer.

摘要翻译： 具有指纹能力的电子数据闪存卡可由主机访问，并且包括连接到闪存设备的处理单元，该闪存设备存储被授权访问数据文件的人员的数据文件和参考指纹数据，用于扫描的指纹传感器 用户的指纹和用于生成可以与存储的参考指纹数据进行比较的输入指纹数据，以及激活以便建立与主计算机的通信的输入 - 输出接口电路。 在一个实施例中，电子数据闪存卡使用USB输入/输出接口电路与主计算机进行通信。

公开(公告)号：US07620769B2

公开(公告)日：2009-11-17

申请号：US11674645

申请日：2007-02-13

申请人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

发明人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/02

CPC分类号： H01R13/629 ,  G06F12/0246 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7209 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： A sliding window of flash blocks is used to reduce wasted space occupied by stale data in a flash memory. The sliding window slides downward over a few flash blocks. The oldest block is examined for valid pages of data, and the valid pages are copied to the end of the sliding window so that the first block has only stale pages. The first block can then be erased and eventually re-used. A RAM usage table contains valid bits for pages in each block in the sliding window. A page's valid bit is changed from an erased, unwritten state to a valid state when data is written to the page. Later, when new host data replaces that data, the old page's valid bit is set to the stale state. A RAM stale-flags table keeps track of pages that are full of stale pages.

摘要翻译： 闪存块的滑动窗口用于减少闪存中过时数据占用的浪费空间。 滑动窗口向下滑过几个闪光块。 检查最旧的块是否有效的数据页面，有效的页面被复制到滑动窗口的末尾，以便第一个块只有过时的页面。 然后可以擦除第一个块并最终重新使用。 RAM使用表包含滑动窗口中每个块中页面的有效位。 当数据写入页面时，页面的有效位从擦除的未写入状态更改为有效状态。 之后，当新的主机数据替换该数据时，旧页面的有效位被设置为陈旧状态。 RAM陈旧标记表可以跟踪页面中已经有过时的页面。