公开(公告)号：US11127697B2

公开(公告)日：2021-09-21

申请号：US16508219

申请日：2019-07-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang ,  Yan Wen Chung ,  Wei Chu Sun

IPC: H01L23/48 ,  H01L29/40 ,  H01L23/66 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.

公开(公告)号：US11101203B2

公开(公告)日：2021-08-24

申请号：US16528325

申请日：2019-07-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/498 ,  H01L21/3205 ,  H05K3/46 ,  H05K3/42

Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure and an intermediate layer. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure. The intermediate layer includes a plurality of sub-layers. Each of the sub-layers is formed from a polymeric material. A boundary is formed between two adjacent sub-layers.

公开(公告)号：US11031382B2

公开(公告)日：2021-06-08

申请号：US16151310

申请日：2018-10-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Pei-Jen Lo ,  Chien-Han Chiu ,  Wen Hung Huang

IPC: H01L27/01 ,  H01L23/00 ,  H01L49/02

Abstract: An electronic device includes: a first insulation layer and a first conductive pillar. The first insulation layer has a first surface and a second surface opposite to the first surface, and the first conductive pillar comprises a first portion and a second portion. The first portion of the first conductive pillar is surrounded by the first insulation layer. The second portion of the first conductive pillar is disposed on the first surface of the first insulation layer. A height of the second portion of the first conductive pillar is equal to or greater than 10% of a height of the first portion of the conductive pillar.

公开(公告)号：US11018120B2

公开(公告)日：2021-05-25

申请号：US16434075

申请日：2019-06-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Mei Huang ,  Shih-Yu Wang ,  I-Ting Lin ,  Wen Hung Huang ,  Yuh-Shan Su ,  Chih-Cheng Lee ,  Hsing Kuo Tien

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/528 ,  H01L23/29

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

公开(公告)号：US10939561B1

公开(公告)日：2021-03-02

申请号：US16552792

申请日：2019-08-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang ,  Min Lung Huang

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/42 ,  H05K3/00 ,  H05K3/46

Abstract: A wiring structure includes a first dielectric layer, a second dielectric layer adjacent to the first dielectric layer, and a conductive region. The first dielectric layer defines a first opening, and the second dielectric layer defines a second opening. The conductive region includes a conductive via filling the first opening and the second opening. The conductive region further includes a first conductive trace embedded in the second dielectric layer and electrically connected with the conductive via. The conductive region includes a sidewall traversing through a thickness of the second dielectric layer with a substantial linear profile. A method of manufacturing a wiring structure is also disclosed.

公开(公告)号：US10796928B1

公开(公告)日：2020-10-06

申请号：US16455548

申请日：2019-06-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46 ,  H01L21/00 ,  H01L21/48 ,  H01L23/498 ,  H01L33/00 ,  H01L33/02 ,  H01L33/22 ,  H01L33/38 ,  H01L33/46 ,  H01L33/50 ,  H01L33/62

Abstract: A wiring structure includes a first unit, a second unit, a first insulation wall, a first redistribution layer and a third unit. The first unit is disposed at a first elevation and having a first circuit layer and a first dielectric layer surrounding the first circuit layer. The second unit is disposed at the first elevation and having a second circuit layer and a second dielectric layer surrounding the second circuit layer. The first insulation wall is disposed between the first unit and the second unit. The first redistribution layer is disposed on the first unit and the second unit, and electrically connected between the first unit and the second unit. The third unit is disposed on the first redistribution layer and having a third circuit layer and a third dielectric layer surrounding the third circuit layer.

公开(公告)号：US10651052B2

公开(公告)日：2020-05-12

申请号：US15870315

申请日：2018-01-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang ,  Yan Wen Chung

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/498 ,  H01L23/66 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.

公开(公告)号：US10468340B2

公开(公告)日：2019-11-05

申请号：US15625920

申请日：2017-06-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang ,  Yan Wen Chung ,  Wei Chu Sun

IPC: H01L23/498 ,  H01L23/00

Abstract: The present disclosure relates to a wiring structure and a semiconductor package. The wiring structure comprises a first wiring pattern, a dielectric layer and a dummy structure. The first wiring pattern includes a conductive land having a width W1 and a surface area A, and a conductive trace having a width W2 and electrically connected to the conductive land, wherein ((W1*W2)/A)*100%≤ about 25%. The dielectric layer covers the first wiring pattern, and the dummy structure is adjacent to the conductive trace.