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公开(公告)号：US08099448B2
公开(公告)日：2012-01-17
申请号：US11266076
申请日：2005-11-02
申请人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
发明人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
CPC分类号： G06F9/30181 , G06F9/30032 , G06F9/3012 , G06F9/30189 , G06F9/3802 , G06F9/3851 , G06F9/3885
摘要： An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.
摘要翻译： 公开了算术逻辑和移位装置，并且包括算术逻辑单元，该算术逻辑单元具有从第一寄存器端口接收第一操作数的第一输入端，从第二寄存器端口接收第二操作数的第二输入端和选择性地提供 以第一操作模式向存储器单元提供存储器地址，并且在第二操作模式中选择性地提供算术输出。 此外，算术逻辑和移位装置包括可编程移位器装置，其具有用于从存储器单元接收数据的第一输入端，用于接收算术输出的第二输入端，接收计算机执行指令的操作码的第三输入端，以及 移位输出以提供移位数据。
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42.发明授权Memory bus output driver of a multi-bank memory device and method therefor 有权多存储存储器件的存储器总线输出驱动器及其方法公开(公告)号：US07505342B2
公开(公告)日：2009-03-17
申请号：US11554522
申请日：2006-10-30
申请人： Jentsung Lin , Ajay Anant Ingle
发明人： Jentsung Lin , Ajay Anant Ingle
IPC分类号： G11C7/00
CPC分类号： G11C29/26 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C8/12 , G11C29/1201 , G11C29/38
摘要： In a particular embodiment, a method is disclosed that includes receiving a first sense output and a second sense output of a sense amplifier at a first tri-state device coupled to a first bus, receiving the first sense output and the second sense output of the sense amplifier at a second tri-state device coupled to a second bus, and selectively activating one of the first tri-state device and the second tri-state device to drive the first bus or the second bus in response to a bus selection input.
摘要翻译： 在一个具体实施例中，公开了一种方法，其包括在耦合到第一总线的第一三态设备处接收读出放大器的第一感测输出和第二感测输出，接收第一感测输出和第二感测输出 耦合到第二总线的第二三态装置处的读出放大器，以及响应于总线选择输入而选择性地激活第一三态装置和第二三态装置之一以驱动第一总线或第二总线。
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公开(公告)号：US09239799B2
公开(公告)日：2016-01-19
申请号：US12146657
申请日：2008-06-26
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , Y02D10/13
摘要： A memory management unit (MMU) for servicing transaction requests from one or more processor threads is described. The MMU can include a translation lookaside buffer (TLB). The TLB can include a storage module and a logic circuit. The storage module can store a bit indicating one of a plurality of interfaces. The bit can be associated with a physical address range. The logic circuit can route a physical address within the physical address range to the one of the plurality of interfaces.
摘要翻译： 描述了用于维护来自一个或多个处理器线程的事务请求的存储器管理单元（MMU）。 MMU可以包括翻译后备缓冲器（TLB）。 TLB可以包括存储模块和逻辑电路。 存储模块可以存储指示多个接口之一的位。 该位可以与物理地址范围相关联。 逻辑电路可以将物理地址范围内的物理地址路由到多个接口之一。
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公开(公告)号：US20120284488A1
公开(公告)日：2012-11-08
申请号：US13099425
申请日：2011-05-03
申请人： Erich James Plondke , Lucian Codrescu , Charles Joseph Tabony , Suresh K. Venkumahanti , Ajay Anant Ingle
发明人： Erich James Plondke , Lucian Codrescu , Charles Joseph Tabony , Suresh K. Venkumahanti , Ajay Anant Ingle
IPC分类号： G06F9/30
CPC分类号： G06F9/30192 , G06F9/30167
摘要： Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 26-bits for example, and the target instruction provides a second set of constant bits, such as 6-bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.
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公开(公告)号：US20120083912A1
公开(公告)日：2012-04-05
申请号：US13314530
申请日：2011-12-08
申请人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
发明人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
CPC分类号： G06F9/30181 , G06F9/30032 , G06F9/3012 , G06F9/30189 , G06F9/3802 , G06F9/3851 , G06F9/3885
摘要： An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.
摘要翻译： 公开了算术逻辑和移位装置，并且包括算术逻辑单元，该算术逻辑单元具有从第一寄存器端口接收第一操作数的第一输入端，从第二寄存器端口接收第二操作数的第二输入端和选择性地提供 以第一操作模式向存储器单元提供存储器地址，并且在第二操作模式中选择性地提供算术输出。 此外，算术逻辑和移位装置包括可编程移位器装置，其具有用于从存储器单元接收数据的第一输入端，用于接收算术输出的第二输入端，接收计算机执行指令的操作码的第三输入端，以及 移位输出以提供移位数据。
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公开(公告)号：US20120011342A1
公开(公告)日：2012-01-12
申请号：US12830494
申请日：2010-07-06
CPC分类号： G06F12/1027 , G06F2212/681 , G06F2212/682 , Y02D10/13
摘要： A system and method to manage a translation lookaside buffer (TLB) is disclosed. In a particular embodiment, a method of managing a first TLB includes in response to starting execution of a memory instruction, setting a first field associated with an entry of the first TLB to indicate use of the entry. The method also includes setting a second field to indicate that the entry in the first TLB matches a corresponding entry in a second TLB.
摘要翻译： 公开了一种用于管理翻译后备缓冲器（TLB）的系统和方法。 在特定实施例中，管理第一TLB的方法包括响应于存储器指令的开始执行，设置与第一TLB的条目相关联的第一字段以指示条目的使用。 该方法还包括设置第二字段以指示第一TLB中的条目与第二TLB中的相应条目匹配。
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公开(公告)号：US20090327647A1
公开(公告)日：2009-12-31
申请号：US12146657
申请日：2008-06-26
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , Y02D10/13
摘要： A memory management unit (MMU) for servicing transaction requests from one or more processor threads is described. The MMU can include a translation lookaside buffer (TLB). The TLB can include a storage module and a logic circuit. The storage module can store a bit indicating one of a plurality of interfaces. The bit can be associated with a physical address range. The logic circuit can route a physical address within the physical address range to the one of the plurality of interfaces.
摘要翻译： 描述了用于维护来自一个或多个处理器线程的事务请求的存储器管理单元（MMU）。 MMU可以包括翻译后备缓冲器（TLB）。 TLB可以包括存储模块和逻辑电路。 存储模块可以存储指示多个接口中的一个的位。 该位可以与物理地址范围相关联。 逻辑电路可以将物理地址范围内的物理地址路由到多个接口之一。
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公开(公告)号：US20090222626A1
公开(公告)日：2009-09-03
申请号：US12039954
申请日：2008-02-29
IPC分类号： G06F12/12
CPC分类号： G06F12/0808 , G06F12/121 , G06F2212/1016 , Y02D10/13
摘要： A system for determining a cache line to replace is described. In one embodiment, the system includes a cache comprising a plurality of cache lines. The system further includes an identifier configured to identify a cache line for replacement. The system also includes a control logic configured to determine a value of the identifier selected from an incrementer, a cache maintenance instruction, or remains the same.
摘要翻译： 描述用于确定要替换的高速缓存行的系统。 在一个实施例中，系统包括包括多个高速缓存行的高速缓存。 该系统还包括被配置为识别用于替换的高速缓存行的标识符。 该系统还包括被配置为确定从增量器，高速缓存维护指令中选择的标识符的值的控制逻辑，或保持相同。
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公开(公告)号：US20090132733A1
公开(公告)日：2009-05-21
申请号：US11942282
申请日：2007-11-19
IPC分类号： G06F3/00 , G06F13/362 , G06F13/00
CPC分类号： G06F13/161
摘要： A system and method for selective preclusion of bus access requests are disclosed. In an embodiment, a method includes determining a bus unit access setting at a logic circuit of a processor. The method also includes selectively precluding a bus unit access request based on the bus unit access setting.
摘要翻译： 公开了用于选择性地排除总线访问请求的系统和方法。 在一个实施例中，一种方法包括确定在处理器的逻辑电路处的总线单元访问设置。 该方法还包括基于总线单元访问设置选择性地排除总线单元访问请求。
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公开(公告)号：US20090119477A1
公开(公告)日：2009-05-07
申请号：US11936269
申请日：2007-11-07
IPC分类号： G06F12/02
CPC分类号： G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： The disclosure includes a method and system of configuring a translation lookaside buffer (TLB). In an embodiment, the TLB includes a first portion and a second portion. The first portion or the second portion may be selectively disabled in response to a value of a TLB configuration indicator.
摘要翻译： 本公开包括配置翻译后备缓冲器（TLB）的方法和系统。 在一个实施例中，TLB包括第一部分和第二部分。 可以响应于TLB配置指示符的值来选择性地禁用第一部分或第二部分。
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