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    Register files for a digital signal processor operating in an interleaved multi-threaded environment
    41.
    发明授权
    Register files for a digital signal processor operating in an interleaved multi-threaded environment 有权
    为交错多线程环境中的数字信号处理器注册文件

    公开(公告)号：US08713286B2

    公开(公告)日：2014-04-29

    申请号：US11115916

    申请日：2005-04-26

    申请人： Muhammad Ahmed ,  Erich Plondke ,  Lucian Codrescu ,  William C. Anderson

    发明人： Muhammad Ahmed ,  Erich Plondke ,  Lucian Codrescu ,  William C. Anderson

    IPC分类号： G06F7/57

    CPC分类号： G06F9/30149 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/3885

    摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.

    摘要翻译： 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。 处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。 多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。 此外，多个寄存器文件中的每一个包括多个数据读取端口，并且多个寄存器堆栈中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。

    Embedded trace macrocell for enhanced digital signal processor debugging operations
    42.
    发明授权
    Embedded trace macrocell for enhanced digital signal processor debugging operations 失效
    嵌入式跟踪宏单元用于增强数字信号处理器调试操作

    公开(公告)号：US08341604B2

    公开(公告)日：2012-12-25

    申请号：US11560339

    申请日：2006-11-15

    申请人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

    发明人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

    IPC分类号： G06F9/44

    CPC分类号： G06F11/3656 ,  G06F9/3005

    摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The method and system improve software instruction debugging operations by capturing real-time information relating to software execution flow and include and instructions and circuitry for operating a core processor process within a core processor. A non-intrusive debugging process operates within a debugging mechanism of a digital signal processor. Non-intrusively monitoring in real time predetermined aspects of software execution occurs with the core processing process and occurs in real-time on the processor. An embedded trace macrocell records selectable aspects of the non-intrusively monitored software execution and generates at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution. The present disclosure controls aspects of the non-intrusive debugging process in response to at least one breakpoint.

    摘要翻译： 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 该方法和系统通过捕获与软件执行流程相关的实时信息来改进软件指令调试操作，并且包括用于在核心处理器内操作核心处理器进程的指令和电路。 非侵入式调试过程在数字信号处理器的调试机制中运行。 非实时监控软件执行的预定方面与核心处理过程相关，并在处理器上实时发生。 嵌入式跟踪宏单元记录非侵入式监视的软件执行的可选方面，并且响应于在非侵入式监视的软件执行的可选择方面内产生的事件而生成至少一个断点。 本公开内容响应于至少一个断点来控制非侵入式调试过程的方面。

    Method and system for variable thread allocation and switching in a multithreaded processor
    43.
    发明授权
    Method and system for variable thread allocation and switching in a multithreaded processor 有权
    多线程处理器中可变线程分配和切换的方法和系统

    公开(公告)号：US07917907B2

    公开(公告)日：2011-03-29

    申请号：US11089474

    申请日：2005-03-23

    申请人： Muhammad Ahmed ,  Sujat Jamil ,  Erich Plondke ,  Lucian Codrescu ,  William C. Anderson

    发明人： Muhammad Ahmed ,  Sujat Jamil ,  Erich Plondke ,  Lucian Codrescu ,  William C. Anderson

    IPC分类号： G06F9/46 ,  G06F15/76

    CPC分类号： G06F9/3851

    摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method further switches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.

    摘要翻译： 用于在通信（例如，CDMA）系统中处理传输的技术。 所公开的主题的一个方面包括用于在多线程处理器上处理指令的方法。 多线程处理器经由多个处理器管线处理多个线程。 该方法包括确定多线程处理器工作的工作频率F的步骤。 然后，该方法确定用于触发多个活动线程之间的处理切换的可变线程切换超时状态。 可变线程切换超时状态改变，使得多个活动线程中的每一个以所分配的频率部分F的频率运行。活动线程运行的分配部分至少部分地被确定，以便优化 操作多线程处理器。 在发生可变线程切换超时状态时，该方法还将处理从主动线程中的第一个切换到下一个活动线程。

    Power-efficient sign extension for booth multiplication methods and systems
    44.
    发明授权
    Power-efficient sign extension for booth multiplication methods and systems 有权
    用于展台乘法方法和系统的高效符号扩展

    公开(公告)号：US07797366B2

    公开(公告)日：2010-09-14

    申请号：US11356359

    申请日：2006-02-15

    申请人： Shankar Krithivasan ,  Christopher Edward Koob ,  William C. Anderson

    发明人： Shankar Krithivasan ,  Christopher Edward Koob ,  William C. Anderson

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5338 ,  G06F7/49994 ,  G06F7/5443

    摘要： Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., code division multiple access) system. Power-efficient sign extension for Booth multiplication processes involves applying a sign bit in a Booth multiplication tree. The sign bit allows the Booth multiplication process to perform a sign extension step. This further involves one-extending a predetermined partial product row of the Booth multiplication tree using a sign bit for preserving the correct sign of the predetermined partial product row. The process and system resolve the signal value of the sign bit by generating a sign-extension bit in the Booth multiplication tree. The sign-extension bit is positioned in a carry-out column to extend the product of the Booth multiplication process. Then, the method and system form a final product from the Booth multiplication tree by adding the carry-out value to the sign bit positioned at least a predetermined column of the Booth multiplication tree. The result is to effectively extend the sum component of the final product with the sign and zero-extending the carry component of the final product.

    摘要翻译： 用于设计和使用数字信号处理器的技术，包括在通信（例如，码分多址）系统中处理传输。 展位乘法过程的功率效率符号扩展涉及在展位乘法树中应用符号位。 符号位允许展位乘法过程执行符号扩展步骤。 这还涉及使用用于保留预定部分乘积行的正确符号的符号位来单扩展布乘除树的预定部分乘积行。 该过程和系统通过在展位乘法树中生成一个符号扩展位来解析符号位的信号值。 符号扩展位位于进位列中以扩展展位乘法过程的乘积。 然后，方法和系统通过将进位值添加到位于布斯乘积树的至少预定列的符号位，从布斯乘积树形成最终产品。 结果是有效地扩展最终产品的总和成分与符号和零扩展最终产品的进位组件。

    Multi-mode instruction memory unit
    45.
    发明授权
    Multi-mode instruction memory unit 有权
    多模式指令存储单元

    公开(公告)号：US07685411B2

    公开(公告)日：2010-03-23

    申请号：US11104115

    申请日：2005-04-11

    申请人： Muhammad Ahmed ,  Lucian Codrescu ,  Erich Plondke ,  William C. Anderson ,  Robert Allan Lester ,  Phillip M. Jones

    发明人： Muhammad Ahmed ,  Lucian Codrescu ,  Erich Plondke ,  William C. Anderson ,  Robert Allan Lester ,  Phillip M. Jones

    IPC分类号： G06F9/00

    CPC分类号： G06F9/325 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/381

    摘要： An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.

    摘要翻译： 指令存储单元包括可操作以存储程序指令的第一存储器结构，以及可操作以存储从第一存储器结构提取的程序指令并且发出用于执行的存储的程序指令的第二存储器结构。 如果前向分支指令的分辨率与其最后一个分辨率相同，则第二存储器结构可操作以识别正向程序重定向构造的重复发出，并发出已经存储在第二存储器结构中的下一个程序指令。 第二存储器结构还可操作以发出反向程序重定向结构，确定目标指令是否存储在第二存储器结构中，如果目标指令存储在第二存储器结构中，则发出目标指令，并从 如果目标指令没有存储在第二存储器结构中的第一存储器结构。

    EMBEDDED TRACE MACROCELL FOR ENHANCED DIGITAL SIGNAL PROCESSOR DEBUGGING OPERATIONS
    46.
    发明申请
    EMBEDDED TRACE MACROCELL FOR ENHANCED DIGITAL SIGNAL PROCESSOR DEBUGGING OPERATIONS 失效
    用于增强数字信号处理器调试操作的嵌入式跟踪

    公开(公告)号：US20080115115A1

    公开(公告)日：2008-05-15

    申请号：US11560339

    申请日：2006-11-15

    申请人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

    发明人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

    IPC分类号： G06F9/44

    CPC分类号： G06F11/3656 ,  G06F9/3005

    摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The method and system improve software instruction debugging operations by capturing real-time information relating to software execution flow and include and instructions and circuitry for operating a core processor process within a core processor. A non-intrusive debugging process operates within a debugging mechanism of a digital signal processor. Non-intrusively monitoring in real time predetermined aspects of software execution occurs with the core processing process and occurs in real-time on the processor. An embedded trace macrocell records selectable aspects of the non-intrusively monitored software execution and generates at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution. The present disclosure controls aspects of the non-intrusive debugging process in response to at least one breakpoint.

    摘要翻译： 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 该方法和系统通过捕获与软件执行流程相关的实时信息来改进软件指令调试操作，并且包括用于在核心处理器内操作核心处理器进程的指令和电路。 非侵入式调试过程在数字信号处理器的调试机制中运行。 非实时监控软件执行的预定方面与核心处理过程相关，并在处理器上实时发生。 嵌入式跟踪宏单元记录非侵入式监视的软件执行的可选方面，并且响应于在非侵入式监视的软件执行的可选择方面内产生的事件而生成至少一个断点。 本公开内容响应于至少一个断点来控制非侵入式调试过程的方面。

    NON-INTRUSIVE, THREAD-SELECTIVE, DEBUGGING METHOD AND SYSTEM FOR A MULTI-THREAD DIGITAL SIGNAL PROCESSOR
    47.
    发明申请
    NON-INTRUSIVE, THREAD-SELECTIVE, DEBUGGING METHOD AND SYSTEM FOR A MULTI-THREAD DIGITAL SIGNAL PROCESSOR 有权
    非线性，螺纹选择性，多线数字信号处理器的调试方法和系统

    公开(公告)号：US20080115113A1

    公开(公告)日：2008-05-15

    申请号：US11560217

    申请日：2006-11-15

    申请人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

    发明人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F11/362

    摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system provide for processing instructions in a multi-threaded process including the use of breakpoint instructions for generating debugging event(s). Generating a debugging event occurs in response to the execution of breakpoint instructions and executes debugging instructions in response to the debugging event. The debugging instructions debug processing instructions in the multi-threaded processor by transitioning at least one or more threads into a debugging mode. The disclosure generates a debugging return for reporting the executing debugging instructions in the subset of the threads of the multi-threaded processor.

    摘要翻译： 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 所公开的方法和系统提供在多线程处理中处理指令，包括使用断点指令来产生调试事件。 响应于断点指令的执行而产生调试事件，并响应调试事件执行调试指令。 调试指令通过将至少一个或多个线程转换为调试模式来调试多线程处理器中的处理指令。 本公开生成用于报告多线程处理器的线程的子集中的执行调试指令的调试返回。