公开(公告)号：US06365943B1

公开(公告)日：2002-04-02

申请号：US09157644

申请日：1998-09-21

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Fred N. Hause

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Fred N. Hause

IPC分类号： H01L2976

CPC分类号： H01L21/823437 ,  Y10S438/947

摘要： A semiconductor transistor which includes a silicon base layer, a gate dielectric formed on the silicon base layer, first and second silicon source/drain structures, first and second spacer structures, and a silicon gate structure is provided. A method for forming the semiconductor transistor may include a semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. A gate dielectric layer is then formed on exposed portions of the silicon base layer over a channel region of the base silicon layer. Portions of the first and second silicon-dielectric stacks located over respective source/drain regions of the base silicon layer are then selectively removed. Silicon is then deposited to fill first and second voids created by the selected removal of the stacks. The silicon deposition also fills a silicon gate region above the gate dielectric over the channel region. Thereafter, an impurity distribution is introduced into the deposited silicon. The deposited silicon is then planarized to physically isolate the silicon within the gate region from the silicon within the first and second voids resulting in the formation of a transistor including a silicon gate structure and first and second source/drain structures.

公开(公告)号：US06245649B1

公开(公告)日：2001-06-12

申请号：US09251923

申请日：1999-02-17

申请人： James F. Buller ,  Jon D. Cheek ,  Daniel Kadosh ,  Derick J. Wristers ,  H. Jim Fulford

发明人： James F. Buller ,  Jon D. Cheek ,  Daniel Kadosh ,  Derick J. Wristers ,  H. Jim Fulford

IPC分类号： H01L2104

CPC分类号： H01L29/105 ,  H01L21/2652

摘要： A method for forming a retrograde impurity profile in a semiconducting substrate is provided. The method comprises forming a sacrificial layer having a thickness in the range of about 10 Å to about 150 Å on the surface of a semiconducting substrate. Thereafter, an ion implantation process is performed wherein dopant impurity ions are directed through the sacrificial layer and into the semiconducting substrate under conditions effective to form a retrograde impurity profile in the semiconducting substrate.

摘要翻译： 提供了一种在半导体衬底中形成逆向杂质分布的方法。 该方法包括在半导体衬底的表面上形成具有在大约至大约的范围内的厚度的牺牲层。 此后，进行离子注入工艺，其中掺杂杂质离子在有效地在半导体衬底中形成逆向杂质分布的条件下引导通过牺牲层并进入半导体衬底。

公开(公告)号：US6150695A

公开(公告)日：2000-11-21

申请号：US741812

申请日：1996-10-30

申请人： Mark Gardner ,  Daniel Kadosh ,  Derick J. Wristers

发明人： Mark Gardner ,  Daniel Kadosh ,  Derick J. Wristers

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L27/01

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： A dual level transistor and a fabrication technique. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed within a local trench etched into a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate and a first transistor formed on the global substrate. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric. The integrated circuit further includes a first inter-substrate dielectric that is formed on the first conductive gate structure and the global substrate. The first inter-substrate dielectric includes a local trench. A first local substrate is formed within the local trench. A second transistor is located within the first local substrate. The second transistor includes a second gate dielectric formed on an upper surface of the first local substrate and a second conductive gate structure formed on an upper surface of the second gate dielectric.

摘要翻译： 双级晶体管和制造技术。 双电平晶体管是集成电路，其中第一晶体管形成在全局电介质的上表面上，并且第二晶体管形成在第一局部衬底的上表面上，使得第二晶体管垂直从第一晶体管 。 第一局部衬底形成在蚀刻到第一衬底间电介质中的局部沟槽内。 通过垂直移位第一和第二晶体管，消除了在典型的单平面工艺中隔离第一和第二晶体管所需的横向分离。 集成电路包括半导体全局基板和形成在全局基板上的第一晶体管。 第一晶体管包括形成在全局衬底的上表面上的第一栅极电介质和形成在第一电介质的上表面上的第一导电栅极结构。 集成电路还包括形成在第一导电栅极结构和全局基板上的第一基板间电介质。 第一基板间电介质包括局部沟槽。 第一局部衬底形成在局部沟槽内。 第二晶体管位于第一局部衬底内。 第二晶体管包括形成在第一局部衬底的上表面上的第二栅极电介质和形成在第二栅极电介质的上表面上的第二导电栅极结构。

公开(公告)号：US6140163A

公开(公告)日：2000-10-31

申请号：US893744

申请日：1997-07-11

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Thomas E. Spikes, Jr.

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Thomas E. Spikes, Jr.

IPC分类号： H01L21/822 ,  H01L21/00 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207

摘要： A high performance semiconductor device structure and method of making the same include a bulk semiconductor substrate and an upper level silicon substrate. The upper level silicon substrate includes a low-K dielectric layer and a silicon substrate layer. The low-K dielectric layer is formed on the bulk semiconductor substrate, the low-K dielectric layer having a dielectric K-value in the range of 2.0-3.8. The silicon substrate layer and low-K dielectric layer are then patterned into the upper level substrate in a first region and the bulk semiconductor substrate is exposed in a second region. A gate oxide layer is formed over the upper level substrate in the first region and over the exposed bulk semiconductor substrate in the second region. Lastly, transistor device formations are formed in the upper level substrate and in the bulk semiconductor substrate.

摘要翻译： 高性能半导体器件结构及其制造方法包括体半导体衬底和上层硅衬底。 上层硅衬底包括低K电介质层和硅衬底层。 低K电介质层形成在体半导体衬底上，低K电介质层的介电K值在2.0-3.8范围内。 然后将硅衬底层和低K电介质层在第一区域中被图案化到上层衬底中，并且在第二区域中暴露体半导体衬底。 栅极氧化物层形成在第一区域中的上层衬底之上并且在第二区域中的暴露的体半导体衬底之上。 最后，晶体管器件形成在上层衬底和体半导体衬底中。

公开(公告)号：US6104064A

公开(公告)日：2000-08-15

申请号：US306508

申请日：1999-05-06

申请人： Daniel Kadosh ,  Mark I. Gardner ,  Michael Duane ,  Jon D. Cheek ,  Fred N. Hause ,  Robert Dawson ,  Brad T. Moore

发明人： Daniel Kadosh ,  Mark I. Gardner ,  Michael Duane ,  Jon D. Cheek ,  Fred N. Hause ,  Robert Dawson ,  Brad T. Moore

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L21/28211 ,  H01L21/28176 ,  H01L29/66659 ,  H01L29/7835

摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.

摘要翻译： 提供了用于产生p沟道和/或n沟道晶体管的各种工艺。 因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。 可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。 据此，本方法采用各种技术形成不对称晶体管。 各种技术采用根据​​所需LDD结果而变化的处理步骤。 首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。 第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。 漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。 第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。 可以存在许多其它修改和替代的处理步骤，其全部在此描述。 不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。 本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

公开(公告)号：US6075258A

公开(公告)日：2000-06-13

申请号：US136177

申请日：1998-08-19

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L29/76

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed into the interlevel dielectric. A second transistor is then formed on the upper surface of the second semiconductor substrate. The second transistor is a spaced distance above the first transistor. The two transistors are a lateral distance apart which is smaller than the distance that can be achieved by conventional fabrication of transistors on the upper surface of the wafer. Transistors are more closely packed which results in an increase in the number of devices produced per wafer.

公开(公告)号：US6069046A

公开(公告)日：2000-05-30

申请号：US979282

申请日：1997-11-26

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28123 ,  H01L21/823814 ,  H01L29/665

摘要： A process is provided for fabricating a transistor in which ion implantation of dopant into source/drain junctions is performed prior to defining the sidewall surfaces of a gate conductor. As such, the sidewall surfaces of the gate conductor are not subjected to damaging bombardment by ions. In one embodiment, a masking layer is patterned above a polysilicon layer dielectrically spaced above a semiconductor substrate. A S/D implant self-aligned to the sidewall surfaces of the masking layer is performed. Portions of the masking layer are removed to reduce the width of the masking layer and to form more closely spaced sidewalls. An LDD implant self-aligned to the new sidewalls of the masking layer is performed. Thereafter, the polysilicon layer is etched to define a gate conductor above and between LDD areas disposed within the substrate. In another embodiment, a sacrificial layer is patterned above a polysilicon layer dielectrically spaced above a semiconductor substrate. A S/D implant self-aligned to the sidewall surfaces of the sacrificial layer and an LDD implant self-aligned to exposed lateral edges of sidewall spacers arranged upon the sidewall surfaces of the sacrificial layer are performed. The polysilicon layer is then etched to define a gate conductor above and between LDD areas arranged within the substrate.

摘要翻译： 提供了一种制造晶体管的工艺，其中在限定栅极导体的侧壁表面之前执行掺杂剂到源极/漏极结的离子注入。 因此，栅极导体的侧壁表面不会受到离子的破坏性轰击。 在一个实施例中，掩模层被图案化在介于半导体衬底之上的多晶硅层之上。 执行与掩模层的侧壁表面自对准的S / D注入。 去除掩模层的一部分以减小掩模层的宽度并形成更紧密间隔的侧壁。 执行与掩模层的新侧壁自对准的LDD注入。 此后，蚀刻多晶硅层以在布置在衬底内的LDD区域之上和之间限定栅极导体。 在另一个实施例中，在半导体衬底上介电间隔的多晶硅层上方构图牺牲层。 执行自对准到牺牲层的侧壁表面的S / D注入和与排列在牺牲层的侧壁表面上的侧壁间隔件的暴露的侧向边缘自对准的LDD注入。 然后蚀刻多晶硅层以在布置在衬底内的LDD区域之上和之间限定栅极导体。

公开(公告)号：US6051459A

公开(公告)日：2000-04-18

申请号：US803730

申请日：1997-02-21

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Frederick N. Hause ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Frederick N. Hause ,  Derick J. Wristers

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842

摘要： A method of making N-channel and P-channel IGFETs is disclosed. The method includes providing a semiconductor substrate with N-type and P-type active regions, forming a gate material over the N-type and P-type active regions, forming a first masking layer over the gate material, wherein the first masking layer includes an opening above a first portion of the gate material over the P-type active region, and the first masking layer covers a second portion of the gate material over the N-type active region, introducing an N-type dopant into the first portion of the gate material without introducing the N-type dopant into the second portion of the gate material, applying a thermal cycle to drive-in and activate the N-type dopant in the first portion of the gate material before introducing any doping into the second portion of the gate material, before introducing any source/drain doping into the N-type active region, and before introducing any source/drain doping into the P-type active region, forming a second masking layer over the gate material, wherein the second masking layer covers portions of the first and second portions of the gate material, applying an etch to form first and second gates from unetched portions of the first and second portions of the gate material, respectively, and forming an N-type source and drain in the P-type active region and forming a P-type source and drain in the N-type active region. Advantageously, a dopant in the gate for the N-channel IGFET can be driven-in and activated at a relatively high temperature without subjecting any source/drain doping to this temperature.

摘要翻译： 公开了制造N沟道和P沟道IGFET的方法。 该方法包括提供具有N型和P型有源区的半导体衬底，在N型和P型有源区上形成栅极材料，在栅极材料上形成第一掩模层，其中第一掩模层包括 在P型有源区上方的栅极材料的第一部分上方的开口，并且第一掩模层覆盖N型有源区上的栅极材料的第二部分，将N型掺杂剂引入到第一部分 栅极材料，而不将N型掺杂剂引入栅极材料的第二部分中，在引入任何掺杂到第二部分之前施加热循环以驱动和激活栅极材料的第一部分中的N型掺杂剂 在向N型有源区域引入任何源极/漏极掺杂之前，在向P型有源区域引入任何源极/漏极掺杂之前，在栅极材料上形成第二掩模层， 在第二掩模层中，分别覆盖栅极材料的第一和第二部分的部分，施加蚀刻以分别从栅极材料的第一和第二部分的未蚀刻部分形成第一和第二栅极，并形成N型源极 并在P型有源区中漏极，并在N型有源区中形成P型源极和漏极。 有利的是，用于N沟道IGFET的栅极中的掺杂剂可以被驱入并在相对较高的温度下被激活，而不会对该温度进行任何源极/漏极掺杂。

公开(公告)号：US6048803A

公开(公告)日：2000-04-11

申请号：US914658

申请日：1997-08-19

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/441

CPC分类号： H01L21/02131 ,  H01L21/02164 ,  H01L21/02321 ,  H01L21/02351 ,  H01L21/31629 ,  H01L21/76801

摘要： A semiconductor device having relatively low permittivity fluorine bearing oxide between conductive lines and a method for fabricating such a device is provided. At least two adjacent conductive lines are formed over a substrate. An oxide layer is formed between the adjacent conductive lines. A mask is formed over the oxide layer and selectively removed to expose a portion of the oxide layer between the adjacent conductive lines. A fluorine bearing species is implanted into the exposed portion of the oxide layer to reduce the permittivity of the oxide layer between the adjacent conductive lines. The permittivity or dielectric constant of the oxide layer between the adjacent conductive lines can, for example, be reduced from about 3.9 to 4.2 to about 3.0 to 3.5.

摘要翻译： 提供了一种在导线之间具有较低介电常数含氟氧化物的半导体器件及其制造方法。 在衬底上形成至少两个相邻的导线。 在相邻的导线之间形成氧化物层。 掩模形成在氧化物层的上方并被选择性地去除以暴露相邻导电线之间的氧化物层的一部分。 将含氟物质注入到氧化物层的暴露部分中以降低相邻导电线之间的氧化物层的介电常数。 相邻导电线之间的氧化物层的介电常数或介电常数例如可以从约3.9至4.2降低至约3.0至3.5。

公开(公告)号：US6037629A

公开(公告)日：2000-03-14

申请号：US28895

申请日：1998-02-24

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Jon D. Cheek

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Jon D. Cheek

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66583 ,  H01L21/76 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/7834

摘要： An IGFET with a gate electrode in a transistor trench adjacent to an isolation trench is disclosed. The trenches are formed in a semiconductor substrate. A gate insulator is on a bottom surface of the transistor trench, insulative spacers are adjacent to opposing sidewalls of the transistor trench, and the gate electrode is on the gate insulator and spacers and is electrically isolated from the substrate. Substantially all of the gate electrode is within the transistor trench. A source and drain in the substrate are beneath and adjacent to the bottom surface of the transistor trench. The isolation trench is filled with an insulator and provides device isolation for the IGFET. Advantageously, the trenches are formed simultaneously using a single etch step.

摘要翻译： 公开了一种在与隔离沟槽相邻的晶体管沟槽中具有栅电极的IGFET。 沟槽形成在半导体衬底中。 栅极绝缘体位于晶体管沟槽的底表面上，绝缘间隔物与晶体管沟槽的相对的侧壁相邻，并且栅极电极位于栅极绝缘体和间隔物上，并与衬底电隔离。 基本上所有的栅电极都在晶体管沟槽内。 衬底中的源极和漏极在晶体管沟槽的底表面下方并且邻近晶体管沟槽的底表面。 绝缘体填充绝缘体，并为IGFET提供器件隔离。 有利地，使用单个蚀刻步骤同时形成沟槽。