公开(公告)号：US5780340A

公开(公告)日：1998-07-14

申请号：US739566

申请日：1996-10-30

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Jon D. Cheek

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Jon D. Cheek

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L29/78

CPC分类号： H01L29/66583 ,  H01L21/76 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/7834

摘要： An IGFET with a gate electrode in a transistor trench adjacent to an isolation trench is disclosed. The trenches are formed in a semiconductor substrate. A gate insulator is on a bottom surface of the transistor trench, insulative spacers are adjacent to opposing sidewalls of the transistor trench, and the gate electrode is on the gate insulator and spacers and is electrically isolated from the substrate. Substantially all of the gate electrode is within the transistor trench. A source and drain in the substrate are beneath and adjacent to the bottom surface of the transistor trench. The isolation trench is filled with an insulator and provides device isolation for the IGFET. Advantageously, the trenches are formed simultaneously using a single etch step.

摘要翻译： 公开了一种在与隔离沟槽相邻的晶体管沟槽中具有栅电极的IGFET。 沟槽形成在半导体衬底中。 栅极绝缘体位于晶体管沟槽的底表面上，绝缘间隔物与晶体管沟槽的相对的侧壁相邻，并且栅极电极位于栅极绝缘体和间隔物上，并与衬底电隔离。 基本上所有的栅电极都在晶体管沟槽内。 衬底中的源极和漏极在晶体管沟槽的底表面下方并且邻近晶体管沟槽的底表面。 绝缘体填充绝缘体，并为IGFET提供器件隔离。 有利地，使用单个蚀刻步骤同时形成沟槽。

公开(公告)号：US5866934A

公开(公告)日：1999-02-02

申请号：US879504

申请日：1997-06-20

申请人： Daniel Kadosh ,  Mark I. Gardner ,  Jon D. Cheek

发明人： Daniel Kadosh ,  Mark I. Gardner ,  Jon D. Cheek

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L27/11

CPC分类号： H01L29/66659 ,  H01L21/28114 ,  H01L21/2815 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/42376 ,  Y10S257/904 ,  Y10S438/947

摘要： An improved series and/or parallel connection of transistors within a logic gate is presented. The improved connection is brought about by a sacrificial structure on which gate conductors are formed adjacent sidewall surfaces of the sacrificial structure. The sacrificial structure thereby provides spacing between the series-connected or parallel-connected transistors. Upon removal of each sacrificial structure, a pair of transistors can be formed by implanting dopant species into the substrate on opposite sides of the spaced conductors. Beneath what was once a sacrificial structure is a shared implant area to which two transistors are coupled either in series or in parallel. By depositing the gate conductor material and then anisotropically removing the material except adjacent the vertical sidewall surfaces, an ultra short gate conductor can be formed concurrent with other gate conductors within a logic gate.

公开(公告)号：US06383872B1

公开(公告)日：2002-05-07

申请号：US09160829

申请日：1998-09-25

申请人： Daniel Kadosh ,  Mark I. Gardner ,  Jon D. Cheek

发明人： Daniel Kadosh ,  Mark I. Gardner ,  Jon D. Cheek

IPC分类号： H01L21335

CPC分类号： H01L29/66659 ,  H01L21/28114 ,  H01L21/2815 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/42376 ,  Y10S257/904 ,  Y10S438/947

摘要： An improved series and/or parallel connection of transistors within a logic gate is presented. The improved connection is brought about by a sacrificial structure on which gate conductors are formed adjacent sidewall surfaces of the sacrificial structure. The sacrificial structure thereby provides spacing between the series-connected or parallel-connected transistors. Upon removal of each sacrificial structure, a pair of transistors can be formed by implanting dopant species into the substrate on opposite sides of the spaced conductors. Beneath what was once a sacrificial structure is a shared implant area to which two transistors are coupled either in series or in parallel. By depositing the gate conductor material and then anisotropically removing the material except adjacent the vertical sidewall surfaces, an ultra short gate conductor can be formed concurrent with other gate conductors within a logic gate.

摘要翻译： 提出了逻辑门内的晶体管的改进的串联和/或并联连接。 改进的连接是通过牺牲结构实现的，在该牺牲结构上，邻近牺牲结构的侧壁表面形成栅极导体。 牺牲结构由此提供串联或并联连接的晶体管之间的间隔。 在去除每个牺牲结构时，可以通过在间隔的导体的相对侧上将掺杂剂物质注入到衬底中来形成一对晶体管。 在一旦牺牲结构之下，就是两个晶体管串联或并联耦合到的共享注入区域。 通过沉积栅极导体材料，然后各向异性除去邻近垂直侧壁表面的材料，可以在逻辑门内与其它栅极导体同时形成超短栅极导体。

公开(公告)号：US6104064A

公开(公告)日：2000-08-15

申请号：US306508

申请日：1999-05-06

申请人： Daniel Kadosh ,  Mark I. Gardner ,  Michael Duane ,  Jon D. Cheek ,  Fred N. Hause ,  Robert Dawson ,  Brad T. Moore

发明人： Daniel Kadosh ,  Mark I. Gardner ,  Michael Duane ,  Jon D. Cheek ,  Fred N. Hause ,  Robert Dawson ,  Brad T. Moore

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L21/28211 ,  H01L21/28176 ,  H01L29/66659 ,  H01L29/7835

摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.

摘要翻译： 提供了用于产生p沟道和/或n沟道晶体管的各种工艺。 因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。 可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。 据此，本方法采用各种技术形成不对称晶体管。 各种技术采用根据​​所需LDD结果而变化的处理步骤。 首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。 第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。 漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。 第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。 可以存在许多其它修改和替代的处理步骤，其全部在此描述。 不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。 本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

公开(公告)号：US6037629A

公开(公告)日：2000-03-14

申请号：US28895

申请日：1998-02-24

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Jon D. Cheek

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Jon D. Cheek

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66583 ,  H01L21/76 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/7834

摘要： An IGFET with a gate electrode in a transistor trench adjacent to an isolation trench is disclosed. The trenches are formed in a semiconductor substrate. A gate insulator is on a bottom surface of the transistor trench, insulative spacers are adjacent to opposing sidewalls of the transistor trench, and the gate electrode is on the gate insulator and spacers and is electrically isolated from the substrate. Substantially all of the gate electrode is within the transistor trench. A source and drain in the substrate are beneath and adjacent to the bottom surface of the transistor trench. The isolation trench is filled with an insulator and provides device isolation for the IGFET. Advantageously, the trenches are formed simultaneously using a single etch step.

摘要翻译： 公开了一种在与隔离沟槽相邻的晶体管沟槽中具有栅电极的IGFET。 沟槽形成在半导体衬底中。 栅极绝缘体位于晶体管沟槽的底表面上，绝缘间隔物与晶体管沟槽的相对的侧壁相邻，并且栅极电极位于栅极绝缘体和间隔物上，并与衬底电隔离。 基本上所有的栅电极都在晶体管沟槽内。 衬底中的源极和漏极在晶体管沟槽的底表面下方并且邻近晶体管沟槽的底表面。 绝缘体填充绝缘体，并为IGFET提供器件隔离。 有利地，使用单个蚀刻步骤同时形成沟槽。

公开(公告)号：US5986283A

公开(公告)日：1999-11-16

申请号：US30751

申请日：1998-02-25

申请人： John J. Bush ,  Jon D. Cheek ,  Mark I. Gardner

发明人： John J. Bush ,  Jon D. Cheek ,  Mark I. Gardner

IPC分类号： H01L21/66 ,  H01L23/58 ,  G01R31/26

CPC分类号： G03F7/70658 ,  H01L22/14 ,  H01L2924/0002

摘要： The present invention advantageously provides a test structure and method for determining how lithographic patterning of transistor gate conductors laterally spaced from conductors affects the operation of transistors which employ the gate conductors. The test structure includes a sequence of gate conductors interposed above and between a respective sequence of source and drain regions. The test structure further includes a sequence of conductors which have been patterned from the same material as the gate conductors. The conductors are spaced an increasing distance from respective gate conductors. The gate conductors extend beyond the respective source and drain regions by varying distances or by the same distance. Lithographic patterning of the gate conductors and the conductors may result in the edges of the gate conductors and the conductors being substantially round and absent of sharp corners. Further, lithographic patterning may lead to a reduction in the lengths of the gate conductors and the conductors. The length of each gate conductor extends along the same axis as the length of the conductor nearest to the gate conductor.

摘要翻译： 本发明有利地提供了一种测试结构和方法，用于确定与导体横向间隔开的晶体管栅极导体的平版印刷图案如何影响采用栅极导体的晶体管的操作。 测试结构包括插入在源极和漏极区域的相应序列之间和之间的栅极导体序列。 该测试结构进一步包括一系列导体，该导体序列由与栅极导体相同的材料构图。 导体与相应的栅极导体间隔开增加的距离。 栅极导体通过变化的距离或相同的距离延伸超过相应的源极和漏极区域。 栅极导体和导体的平版印刷图案可能导致栅极导体和导体的边缘基本上圆形且不存在锐角。 此外，光刻图案化可能导致栅极导体和导体的长度减小。 每个栅极导体的长度沿与导体最接近的导体的长度相同的轴线延伸。

公开(公告)号：US5926693A

公开(公告)日：1999-07-20

申请号：US788376

申请日：1997-01-27

申请人： Mark I. Gardner ,  Fred N. Hause ,  Jon D. Cheek

发明人： Mark I. Gardner ,  Fred N. Hause ,  Jon D. Cheek

IPC分类号： H01L27/07 ,  H01L27/088 ,  H01L21/00

CPC分类号： H01L27/0705 ,  H01L27/088

摘要： A semiconductor process in which a trench transistor is formed between a pair of planar transistors such that the source/drain regions of the trench transistor are shared with the source/drain regions of the planar transistors. A substrate is provided and first and second planar transistors are formed upon the upper surface of the substrate. The gate dielectric of the trench transistor is vertically displaced below the upper surface of the substrate. The trench transistor shares a first shared source/drain structure with the first planar transistor and a second shared source/drain structure with the second planar transistor. The formation of the trench transistor preferably includes the steps of etching a trench into the substrate, thermally oxidizing a floor of the trench to form a trench gate dielectric, and filling the trench with a conductive material to form a trench gate structure. The trench floor is vertically displaced below the upper surface of the substrate by a trench depth. The trench depth is preferably greater than a junction depth of the source/drain structures. In one embodiment, the formation of the trench transistor further includes, prior to the thermal oxidation of the trench floor, forming first and second ldd structures within the first and second trench ldd regions of the substrate. The first and second trench ldd structures provide conductive paths that extend from a trench channel region located beneath the trench floor to the first and the second shared source/drain structures respectively.

摘要翻译： 一种半导体工艺，其中沟槽晶体管形成在一对平面晶体管之间，使得沟槽晶体管的源极/漏极区域与平面晶体管的源极/漏极区域共享。 提供衬底，并且在衬底的上表面上形成第一和第二平面晶体管。 沟槽晶体管的栅极电介质在衬底的上表面下方垂直位移。 沟槽晶体管与第一平面晶体管共享第一共享源极/漏极结构，并且与第二平面晶体管共享第二共享源极/漏极结构。 沟槽晶体管的形成优选地包括以下步骤：将沟槽蚀刻到衬底中，热氧化沟槽的底部以形成沟槽栅极电介质，并用导电材料填充沟槽以形成沟槽栅极结构。 沟槽底部通过沟槽深度在衬底的上表面下方垂直移位。 沟槽深度优选地大于源极/漏极结构的结深度。 在一个实施例中，沟槽晶体管的形成还包括在沟槽底板的热氧化之前，在衬底的第一和第二沟槽区域内形成第一和第二层结构。 第一和第二沟槽层结构提供从位于沟槽底部下方的沟槽沟道区域分别延伸到第一和第二共享源极/漏极结构的导电路径。

公开(公告)号：US6118163A

公开(公告)日：2000-09-12

申请号：US17720

申请日：1998-02-04

申请人： Mark I. Gardner ,  Derick J. Wristers ,  Jon D. Cheek

发明人： Mark I. Gardner ,  Derick J. Wristers ,  Jon D. Cheek

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/28061 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

摘要： An integrated circuit transistor and method of making the same are provided. The transistor includes a substrate, first and second source/drain regions, and a gate electrode stack coupled to the substrate. The gate electrode stack is fabricated by forming a first insulating layer on the substrate, forming a first conductor layer on the first insulating layer, and forming a metal layer on the first conductor layer. A second insulating layer, such as an interlevel dielectric layer, is coupled to the substrate adjacent to the gate electrode stack. Sidewall spacers and LDD processing may be incorporated. The transistor and method integrate metal and polysilicon into a self-aligned gate electrode stack.

摘要翻译： 提供集成电路晶体管及其制造方法。 晶体管包括衬底，第一和第二源极/漏极区域以及耦合到衬底的栅电极堆叠。 通过在基板上形成第一绝缘层，在第一绝缘层上形成第一导体层，在第一导体层上形成金属层，制作栅电极堆叠。 诸如层间电介质层的第二绝缘层耦合到与栅电极堆叠相邻的衬底。 可以并入侧壁间隔物和LDD处理。 晶体管和方法将金属和多晶硅集成到自对准栅极电极堆叠中。

公开(公告)号：US06225201B1

公开(公告)日：2001-05-01

申请号：US09433801

申请日：1999-11-03

申请人： Mark I. Gardner ,  Derrick J. Wristers ,  Jon D. Cheek ,  Thomas E. Spikes, Jr.

发明人： Mark I. Gardner ,  Derrick J. Wristers ,  Jon D. Cheek ,  Thomas E. Spikes, Jr.

IPC分类号： H01L213205

CPC分类号： H01L29/517 ,  H01L21/0338 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/2815 ,  H01L21/28194 ,  H01L21/31144 ,  H01L29/6659 ,  H01L29/66659 ,  Y10S438/947

摘要： An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length dictated by the width of a sidewall spacer which either embodies a gate conductor for the transistor or is used to pattern an underlying gate conductor. In one embodiment, the sidewall spacers are formed upon and extending laterally from the opposed sidewall surfaces of a sacrificial material. The sidewall surfaces of the sacrificial material are defined by forming the sacrificial material within an opening interposed laterally between vertically extending sidewalls which bound a gate dielectric. An upper portion of the gate dielectric is removed to partially expose the sidewall surfaces arranged at the periphery of the sacrificial material. Polysilicon spacers are formed exclusively upon the sidewall surfaces of the sacrificial material to define a pair of gate conductors having relatively small lateral widths. Portions of the gate dielectric not arranged exclusively beneath the gate conductors may be selectively removed. In another embodiment, sidewall spacers are used to protect select regions of a polysilicon gate material arranged exclusively underneath the spacers from being etched. The sidewall spacers are formed upon and extending laterally from sidewall surfaces arranged at the periphery of an opening which extends through a masking or sacrificial material to an underlying polysilicon gate material. The sidewall spacers are sacrificial in that they are removed from the semiconductor topography after they have served their purpose of masking the underlying polysilicon gate material.

摘要翻译： 提供了一种集成电路制造工艺，用于形成具有由侧壁间隔物的宽度所规定的超短沟道长度的晶体管，该侧壁间隔物体现了晶体管的栅极导体或用于对下面的栅极导体进行图案化。 在一个实施例中，侧壁间隔件形成在牺牲材料的相对的侧壁表面上并从牺牲材料的相对侧壁表面延伸。 牺牲材料的侧壁表面通过在封闭栅极电介质的垂直延伸侧壁之间横向插入的开口内形成牺牲材料来限定。 去除栅极电介质的上部以部分地暴露设置在牺牲材料的周边处的侧壁表面。 专门在牺牲材料的侧壁表面上形成多晶硅间隔物，以限定具有相对小的横向宽度的一对栅极导体。 可以选择性地去除不排列在栅极导体下方的栅极电介质的部分。 在另一个实施例中，侧壁间隔件用于保护专门在间隔物下方布置的多晶硅栅极材料的选择区域被蚀刻。 侧壁间隔件形成在侧壁表面上并且从侧壁表面延伸出来，该侧壁表面布置在开口的周边，该开口延伸穿过掩模或牺牲材料到下面的多晶硅栅极材料。 侧壁间隔物是牺牲的，因为它们已经用于掩盖下面的多晶硅栅极材料的目的，从半导体拓扑图中去除它们。

公开(公告)号：US06191446B1

公开(公告)日：2001-02-20

申请号：US09035780

申请日：1998-03-04

申请人： Mark I. Gardner ,  John J. Bush ,  Jon D. Cheek

发明人： Mark I. Gardner ,  John J. Bush ,  Jon D. Cheek

IPC分类号： H01L2976

CPC分类号： H01L29/66666 ,  H01L29/665 ,  H01L29/7827 ,  Y10S257/90

摘要： A process is provided for forming a transistor in which the channel length is controlled by the depth of a trench etched into a semiconductor substrate. A masking layer extending across the substrate and a portion of the substrate are etched simultaneously to form the trench. A gate dielectric is formed upon the opposed sidewall surfaces of the trench. A pair of gate conductors are then formed upon the exposed lateral surfaces of the gate dielectric and the masking layer. Subsequently, an unmasked region of the substrate underneath the trench is implanted with dopant species and then annealed to form a source junction. The anneal temperature is preferably sufficient to cause the dopant species in the source junction to migrate laterally past the opposed sidewall surfaces of the trench. Drain junctions may subsequently be formed within the substrate a spaced distance above the source region on opposite sides of the trench. The physical channel length of the resulting transistors is thus defined as the distance between a source region and an overlying drain region. The channel of each transistor is spaced laterally from a gate conductor by a gate dielectric.

摘要翻译： 提供了一种用于形成晶体管的工艺，其中沟道长度被蚀刻到半导体衬底中的沟槽的深度控制。 同时蚀刻跨过衬底延伸的掩模层和衬底的一部分以形成沟槽。 栅极电介质形成在沟槽的相对的侧壁表面上。 然后在栅极电介质和掩蔽层的暴露的侧表面上形成一对栅极导体。 随后，在沟槽下面的衬底的未掩蔽区域注入掺杂剂种类，然后退火以形成源极结。 退火温度优选足以使源极结中的掺杂物质横向迁移通过沟槽的相对的侧壁表面。 随后可以在衬底的相对侧上的源极区域上方间隔开距离处形成漏极结。 因此，所得晶体管的物理沟道长度被定义为源极区域和上覆漏极区域之间的距离。 每个晶体管的沟道通过栅极电介质与栅极导体横向隔开。