公开(公告)号：US06438627B1

公开(公告)日：2002-08-20

申请号：US09076561

申请日：1998-05-12

申请人： Brian S. Hausauer ,  Siamak Tavallaei

发明人： Brian S. Hausauer ,  Siamak Tavallaei

IPC分类号： G06F1314

CPC分类号： G06F13/28 ,  G06F12/0215

摘要： An apparatus is disclosed for predicting and making available in advance certain information, namely the address signals from an expansion bus, so as to relax the timing requirement of the burst transfer cycle. A decoder responds to the control signals of the expansion bus to detect the start and the end of a burst transfer cycle. The decoder controls a counter, which stores the initial address signals of the expansion bus at the start of the burst transfer cycle and predicts the initial address signals by incrementing the address signals during the burst transfer cycle. A multiplexer couples either the predicted address signal to the multiplexer output during the burst transfer cycle or the address signal of the EISA bus to the multiplexer output when the computer system is not performing the EMB burst transfer cycle. In another aspect of the present invention, the low order address signal of the bus is predicted using a second counter. The output of the second counter is merged into the low order address signal of the bus interface devices to properly index the second word of the burst transfer cycle.

摘要翻译： 公开了一种用于预测并提供某些信息（即来自扩展总线的地址信号）以便放松突发传送周期的定时要求的装置。 解码器响应扩展总线的控制信号以检测突发传送周期的开始和结束。 解码器控制计数器，该计数器在突发传送周期开始时存储扩展总线的初始地址信号，并通过在突发传送周期期间递增地址信号来预测初始地址信号。 当计算机系统不执行EMB突发传输周期时，多路复用器将突发传送周期期间的预测地址信号与EISA总线的地址信号耦合到多路复用器输出。 在本发明的另一方面，使用第二计数器预测总线的低阶地址信号。 第二计数器的输出被合并到总线接口设备的低位地址信号中，以适当地对突发传送周期的第二个字进行索引。

公开(公告)号：US06385682B1

公开(公告)日：2002-05-07

申请号：US09313220

申请日：1999-05-17

申请人： Theodore F. Emerson ,  Siamak Tavallaei ,  John V. Butler

发明人： Theodore F. Emerson ,  Siamak Tavallaei ,  John V. Butler

IPC分类号： G06F1516

CPC分类号： G06F11/2294

摘要： A computer system, such as a server disposed in an enterprise, accessible from a remote terminal for remote management applications. The computer system includes a remote console functionality assist logic structure for effectuating the sending and receiving-of signals from the remote terminal. The remote console functionality assist logic structure is controlled by a dedicated processor that receives interrupts therefrom in response to a remote management application. The processor can also control one or more peripheral devices provided in the computer system, wherein the controlled peripheral device or devices are disposed up-stream or down-stream from the processor.

摘要翻译： 计算机系统，例如设置在企业中的服务器，可从远程终端访问用于远程管理应用。 计算机系统包括用于实现从远程终端发送和接收信号的远程控制台功能辅助逻辑结构。 远程控制台功能辅助逻辑结构由专用处理器控制，专用处理器响应于远程管理应用从其接收中断。 处理器还可以控制在计算机系统中提供的一个或多个外围设备，其中受控的外围设备或设备从处理器的上游或下游设置。

公开(公告)号：US06360291B1

公开(公告)日：2002-03-19

申请号：US09241203

申请日：1999-02-01

申请人： Siamak Tavallaei

发明人： Siamak Tavallaei

IPC分类号： G06F1314

CPC分类号： G06F13/4027

摘要： A computer system with an Intelligent Input/Output architecture having a dynamic device blocking mechanism for hiding at least a portion of peripheral devices. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, an input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices operably connected to the I/O bus for transferring data in I/O transactions controlled by an IOP resource. A plurality of I/O bus signals are supplied to the device blocking module for determining which bus master owns the I/O bus in order to initiate a bus cycle. If the bus cycle is about to be commenced on behalf of the host processor and its OS, an enable signal associated with the selected peripheral device is negated until the cycle is completed. If, on the other hand, the bus cycle is initiated by the IOP, the enable signal is asserted for the duration of the transaction, which signal, otherwise, remains in a negated state.

摘要翻译： 具有智能输入/输出架构的计算机系统具有用于隐藏外围设备的至少一部分的动态设备阻塞机制。 计算机系统包括用于执行主机操作系统的主机处理器，设置在主机总线上的主机处理器，经由主机到总线桥接器可操作地耦合到主机总线的输入/输出（I / O）总线， 以及可操作地连接到I / O总线的用于在由IOP资源控制的I / O事务中传送数据的多个外围设备。 多个I / O总线信号被提供给器件阻塞模块，用于确定哪个总线主机拥有I / O总线以便启动总线周期。 如果总线周期即将代表主处理器及其OS开始，则与选定的外围设备相关联的使能信号被否定，直到该周期完成。 另一方面，如果由IOP启动总线周期，则在交易持续时间内使能使能信号，否则，该信号保持在否定状态。

公开(公告)号：US6061754A

公开(公告)日：2000-05-09

申请号：US882615

申请日：1997-06-25

申请人： Darren J. Cepulis ,  Siamak Tavallaei ,  Alexander C. Ekrot

发明人： Darren J. Cepulis ,  Siamak Tavallaei ,  Alexander C. Ekrot

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4022

摘要： A data bus structure is disclosed. The structure includes a data bus having a bus agent connection point and a bus switch to selectively connect or disconnect the connection point to or from the data bus. A method of reconfiguring a data bus structure is also disclosed. The method includes providing two bus agent connection points on a data bus and a bus switch between the bus agent connection points and selecting the number of bus agent connection points on the bus by controlling the state of the bus switch.

摘要翻译： 公开了一种数据总线结构。 该结构包括具有总线代理连接点的数据总线和用于选择性地连接或断开与数据总线的连接点的总线开关。 还公开了一种重新配置数据总线结构的方法。 该方法包括在数据总线上提供两个总线代理连接点以及总线代理连接点之间的总线开关，并通过控制总线开关的状态选择总线上总线代理连接点的数量。

公开(公告)号：US5987538A

公开(公告)日：1999-11-16

申请号：US911608

申请日：1997-08-15

申请人： Siamak Tavallaei ,  Gary B. Kotzur

发明人： Siamak Tavallaei ,  Gary B. Kotzur

IPC分类号： G06F13/24 ,  G06F13/14

CPC分类号： G06F13/24

摘要： Apparatus, and an associated method, for requesting initiation of generation of an interrupt at an I/O APIC (input/output advanced programmable interrupt controller) of a multi-processor computer system. Initiation of generation of the inter-processor interrupt is requested by a peripheral component device, such as a PCI bus controller, not directly connected to an APIC bus extending to interrupt controllers associated with each of the processors of the multi-processor computer system. The interrupt permitted to be initiated by the peripheral component device includes, inter alia, a remote read request.

摘要翻译： 用于请求在多处理器计算机系统的I / O APIC（输入/输出高级可编程中断控制器）处产生中断的装置和相关方法。 开始生成处理器间中断是由外部组件设备（例如PCI总线控制器）请求的，该PCI总线控制器不直接连接到延伸到与多处理器计算机系统的每个处理器相关联的中断控制器的APIC总线。 允许由外围组件设备启动的中断尤其包括远程读取请求。

公开(公告)号：US5933614A

公开(公告)日：1999-08-03

申请号：US775392

申请日：1996-12-31

申请人： Siamak Tavallaei ,  Daniel Stuart Hull

发明人： Siamak Tavallaei ,  Daniel Stuart Hull

IPC分类号： G06F11/20 ,  G06F11/00 ,  G06F11/273 ,  G06F11/30 ,  G06F11/34 ,  G06F13/24 ,  G06F13/362 ,  G06F13/00

CPC分类号： G06F11/3495 ,  G06F11/0748 ,  G06F11/0793 ,  G06F11/349 ,  G06F11/20 ,  G06F11/2025 ,  G06F11/2294

摘要： A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and/or keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare. In addition to detecting errors and performing survival and maintenance operations, the SMC enhances system performance during normal operations by supporting master-target priority determinations to more efficiently arbitrate mastership of system busses such as the PCI bus.

公开(公告)号：US5907689A

公开(公告)日：1999-05-25

申请号：US777826

申请日：1996-12-31

申请人： Siamak Tavallaei ,  Gary B. Kotzur

发明人： Siamak Tavallaei ,  Gary B. Kotzur

IPC分类号： G06F13/362 ,  G06F13/00

CPC分类号： G06F13/362

摘要： A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and/or keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare. In addition to detecting errors and performing survival and maintenance operations, the SMC enhances system performance during normal operations by supporting master-target priority determinations to more efficiently arbitrate mastership of system busses such as the PCI bus.

摘要翻译： 用于主机服务器系统的系统管理模块（SMM）包括连接到系统管理本地总线的系统管理处理器（SMP）。 系统管理本地总线通过系统管理中心（SMC）连接到系统PCI总线。 SMC包括PCI总线的主要仲裁单元，还包括系统管理本地总线的仲裁器。 SMM包括连接到系统管理本地总线的视频控制器和/或键盘和鼠标控制器，以支持SMM的远程安装。 SMC包括监视PCI周期的逻辑，并在发生系统错误时发出错误信号。 SMC还通过屏蔽失败设备的请求，授权和中断线来隔离故障组件。 此外，如果提供备用组件，则SMC允许动态切换到备用组件。 除了检测错误和执行生存和维护操作之外，SMC通过支持主目标优先级确定来提高系统性能，从而更有效地仲裁系统总线（如PCI总线）的掌握。