公开(公告)号：US08504882B2

公开(公告)日：2013-08-06

申请号：US12884305

申请日：2010-09-17

Applicant: Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Siriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

Inventor： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Siriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

IPC: G06F11/00

CPC classification number: G06F11/267

Abstract: An integrated circuit (“IC”) includes circuitry for use in testing a serial data signal. One such IC includes circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. One such IC also includes circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. Such an IC provides output signals indicative of results of its operations. One such IC operates in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

Abstract translation: 集成电路（“IC”）包括用于测试串行数据信号的电路。 一个这样的IC包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度来发送串行数据信号的电路。 一个这样的IC还包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 这样的IC提供指示其操作结果的输出信号。 一个这样的IC以各种模式运行，以执行或至少模拟示波器，误码率测试仪等的功能，用于测试关于抖动容差，噪声容限等的信号和电路。

公开(公告)号：US08416001B2

公开(公告)日：2013-04-09

申请号：US13083431

申请日：2011-04-08

Applicant: Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Yanjing Ke

Inventor： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Yanjing Ke

IPC: H03K3/017 ,  H03K5/04 ,  H03K7/08

CPC classification number: H03K5/1565 ,  H03K3/017 ,  H03K5/12 ,  H03M9/00

Abstract: A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.

Abstract translation: 发射机电路可操作以响应于第一周期性信号提供输出信号。 多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。 多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。 采样器电路可操作以在第一操作阶段产生所选信号的第一采样。 采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。 占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

公开(公告)号：US08290750B1

公开(公告)日：2012-10-16

申请号：US13036437

申请日：2011-02-28

Applicant: Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

Inventor： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

IPC: H03F1/26

CPC classification number: H03K5/19 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778

Abstract: Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

Abstract translation: 串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。 可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。 用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。 因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。 可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。 该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

公开(公告)号：US20120072785A1

公开(公告)日：2012-03-22

申请号：US12884923

申请日：2010-09-17

Applicant: Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

Inventor： Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

IPC: G06F11/00

CPC classification number: H04L1/203 ,  G01R31/3171

Abstract: An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

Abstract translation: 提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。 在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。 在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。 在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。 在一个实现中，BER检查器是专用的BER检查器。 在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。

公开(公告)号：US20120072784A1

公开(公告)日：2012-03-22

申请号：US12884305

申请日：2010-09-17

Applicant: Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Sriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

Inventor： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Sriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

IPC: G06F11/00

CPC classification number: G06F11/267

Abstract: An integrated circuit (“IC”) may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

Abstract translation: 集成电路（“IC”）可以包括用于测试串行数据信号的电路。 IC可以包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度发送串行数据信号的电路。 IC还可以包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 IC可以提供指示其操作结果的输出信号。 IC可以以各种模式运行，以执行或至少模拟示波器，误码率测试仪等功能，用于在抖动容限，噪声容限等方面测试信号和电路。

公开(公告)号：US07956695B1

公开(公告)日：2011-06-07

申请号：US12729356

申请日：2010-03-23

Applicant: Weiqi Ding ,  Mengchi Liu

Inventor： Weiqi Ding ,  Mengchi Liu

IPC: H03B5/12

CPC classification number: H03K3/0322

Abstract: A voltage-controlled oscillator operates at high frequency without high gain by dividing the frequency range into a plurality of subranges, which preferably are substantially equal in size. Within any subrange, the full extent of variation in the control signal changes the frequency only by the extent of the subrange. The gain is thus substantially equal to the gain one would expect for the full frequency range, divided by the number of subranges. The subrange may be selected manually, or by an initial calibration process. In one embodiment, the oscillator includes a voltage-to-current converter and a current-controlled oscillator, with a current mirror arrangement. In that embodiment, selection of the subrange may be controlled by turning on the correct number of current legs.

Abstract translation: 压控振荡器通过将频率范围分成多个子范围而在高频率下无高增益，其优选地基本上等于大小。 在任何子范围内，控制信号的全部变化范围仅通过子范围的程度改变频率。 因此，增益基本上等于全频率范围预期的增益除以子范围的数量。 可以手动或通过初始校准过程选择子范围。 在一个实施例中，振荡器包括具有电流镜布置的电压 - 电流转换器和电流控制振荡器。 在该实施例中，可以通过打开当前腿的正确数目来控制子范围的选择。

公开(公告)号：US07924046B1

公开(公告)日：2011-04-12

申请号：US12776871

申请日：2010-05-10

Applicant: Weiqi Ding

Inventor： Weiqi Ding

IPC: H03K17/16

CPC classification number: H04L25/0286

Abstract: Pre-emphasis may be able to operate in either of two modes. In a first mode, when one bit has a same value as the bit that immediately preceded it, an output signal for said one bit is based on a first electrical current reduced by a second electrical current. Otherwise the output signal for said one bit is based on the first current without regard for the second current. The second mode may be similar to the first mode when said one bit has the same value as the immediately preceding bit; but otherwise the output signal for said one bit is based on the first current increased by the second current. As an alternative to using the immediately preceding bit (as in the above “post-tap” operation), the immediately succeeding (following) bit may be used in generally the same way (in so-called “pre-tap” operation).

Abstract translation: 预加重可能能够以两种模式中的任一种运行。 在第一模式中，当一位与其之前的位具有相同的值时，所述一位的输出信号基于由第二电流减小的第一电流。 否则，所述一位的输出信号基于第一电流而不考虑第二电流。 当所述一个比特具有与前一比特相同的值时，第二模式可以类似于第一模式; 否则所述一位的输出信号基于第二电流增加的第一电流。 作为使用紧接在前的位（如在上述“后抽头”操作中）的替代方案，可以以大致相同的方式（在所谓的“预抽头”操作）中使用紧随其后的（后续）位。

公开(公告)号：US07915941B1

公开(公告)日：2011-03-29

申请号：US12496387

申请日：2009-07-01

Applicant: Mingde Pan ,  Weiqi Ding

Inventor： Mingde Pan ,  Weiqi Ding

IPC: H03H11/16

CPC classification number: H03H11/20 ,  H03J2200/10

Abstract: A phase interpolator circuit includes first and second low pass filter circuits and a multiplier circuit. The first low pass filter circuit increases a common mode voltage of a clock signal to generate a first varying signal. The second low pass filter circuit increases a common mode voltage of a clock signal to generate a second varying signal. The first low pass filter circuit can include a first variable capacitance, and the second low pass filter circuit can include a second variable capacitance. The multiplier circuit has a first input coupled to the first low pass filter circuit and a second input coupled to the second low pass filter circuit. The multiplier circuit generates a third varying signal in response to the first and the second varying signals. The phase interpolator circuit generates a phase shift in the third varying signal.

Abstract translation: 相位插值器电路包括第一和第二低通滤波器电路和乘法器电路。 第一低通滤波器电路增加时钟信号的共模电压以产生第一变化信号。 第二低通滤波器电路增加时钟信号的共模电压以产生第二变化信号。 第一低通滤波器电路可以包括第一可变电容，并且第二低通滤波器电路可以包括第二可变电容。 乘法器电路具有耦合到第一低通滤波器电路的第一输入和耦合到第二低通滤波器电路的第二输入。 乘法器电路响应于第一和第二变化信号产生第三变化信号。 相位插值器电路在第三变化信号中产生相移。

公开(公告)号：US20090154591A1

公开(公告)日：2009-06-18

申请号：US12002540

申请日：2007-12-17

Applicant: Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Weiqi Ding

Inventor： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Weiqi Ding

IPC: H04L27/00

CPC classification number: H04L25/028

Abstract: Transmitter driver circuitry for outputting a high-speed serial data signal (e.g., in the range of about 10 gigabits per second or higher) includes H-tree driver circuitry having only a main driver stage and a post-tap driver stage. At least one transistor in the H-tree driver circuitry is constructed and connected to provide electrostatic discharge protection. PMOS and NMOS current sources are used for the H-tree driver circuitry to enhance power supply noise rejection.

Abstract translation: 用于输出高速串行数据信号（例如，在大约10吉比特每秒或更高的范围内）的发射器驱动器电路包括仅具有主驱动器级和抽头后驱动级的H树驱动器电路。 H树驱动器电路中的至少一个晶体管被构造和连接以提供静电放电保护。 PMOS和NMOS电流源用于H-tree驱动器电路，以增强电源噪声抑制。

公开(公告)号：US20090154542A1

公开(公告)日：2009-06-18

申请号：US12002539

申请日：2007-12-17

Applicant: Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Shumarayev

Inventor： Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Shumarayev

IPC: H03H7/30

CPC classification number: H04L25/03885 ,  H04L7/0054 ,  H04L25/03019 ,  H04L25/03878

Abstract: Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

Abstract translation: 用于接收高速串行数据信号（例如，具有在约10Gpbs及更高的范围内的比特率）的电路包括仅具有两个串联连接级的两级连续时间线性均衡器。 可以提供相位检测器电路用于接收均衡器的串行输出，并将该输出中的连续比特对转换为连续并行形式的位对。 可以提供进一步的解复用电路以将并行形式位对的连续组分解成最终并行位组，在位数（例如，64个并行位）方面可能相当大。 本发明的另一方面涉及用于从相对大的并行数据比特组相对于高速串行数据输出信号有效地进行反向的多路复用器电路。