公开(公告)号：US07352835B1

公开(公告)日：2008-04-01

申请号：US10668900

申请日：2003-09-22

申请人： Kazi Asaduzzaman ,  Wilson Wong

发明人： Kazi Asaduzzaman ,  Wilson Wong

IPC分类号： H04L7/02

CPC分类号： H04L7/0338 ,  H03L7/0807 ,  H03L7/087

摘要： Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference clock mode and data mode, can be controlled by two control signals that signal the CDR circuitry to automatically switch between reference clock mode and data mode, to operate only in reference clock mode, or to operate only in data mode. The control signals can be set by a programmable logic device (PLD), by circuitry external to the PLD, or by user input. A dynamically adjustable parts per million (PPM) detector can also be provided in the CDR circuitry to signal when processing of data during the reference clock mode is completed.

摘要翻译： 可以为时钟数据恢复（CDR）电路提供动态支持，以改变由不同协议的接口引起的数据速率。 以参考时钟模式和数据模式工作的CDR电路可以由两个控制信号控制，这两个信号指示CDR电路在参考时钟模式和数据模式之间自动切换，仅在参考时钟模式下工作，或仅在 数据模式。 控制信号可由可编程逻辑器件（PLD），PLD外部电路或用户输入设置。 也可以在CDR电路中提供动态可调节的百万分之一（PPM）检测器，以在参考时钟模式完成期间处理数据时发出信号。

公开(公告)号：US20070025436A1

公开(公告)日：2007-02-01

申请号：US11192539

申请日：2005-07-28

申请人： Sergey Shumarayev ,  Wilson Wong ,  Rakesh Patel

发明人： Sergey Shumarayev ,  Wilson Wong ,  Rakesh Patel

IPC分类号： H03H7/30

CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03573

摘要： Equalization circuitry for receiving a digital data signal includes both feed-forward equalizer (“FFE”) circuitry and decision-feedback equalizer (“DFE”) circuitry. The FFE circuitry may be used to give the DFE circuitry a signal that is at least minimally adequate for proper start-up of the DFE circuitry. Thereafter, more of the burden of the equalization task may be shifted from the FFE circuitry to the DFE circuitry.

摘要翻译： 用于接收数字数据信号的均衡电路包括前馈均衡器（“FFE”）电路和判决反馈均衡器（“DFE”）电路。 FFE电路可以用于给DFE电路提供至少最不足以适当启动DFE电路的信号。 此后，均衡任务的更多负担可能从FFE电路转移到DFE电路。

公开(公告)号：US07132847B1

公开(公告)日：2006-11-07

申请号：US10708303

申请日：2004-02-24

申请人： Wilson Wong ,  Sergey Shumarayev ,  Rakesh Patel

发明人： Wilson Wong ,  Sergey Shumarayev ,  Rakesh Patel

IPC分类号： H03K19/003

CPC分类号： H03K17/6872 ,  H03K17/164

摘要： A programmable technique is used to control the slew rate of a differential output buffer. A method controls the slew rate (SR) by changing an “on” resistance of the switches used to steer the current. This can be accomplished by (i) using different size switches or (ii) changing the slew rate of the predrivers which drive the final switches. The latter approach has the advantage that it only temporarily increases the “on” resistance, which does not cause any headroom problems after the transient. A specific application is for the differential outputs of a programmable logic integrated circuits.

摘要翻译： 可编程技术用于控制差分输出缓冲器的转换速率。 一种方法通过改变用于转向电流的开关的“导通”电阻来控制转换速率（SR）。 这可以通过（i）使用不同尺寸的开关或（ii）改变驱动最终开关的预驱动器的转换速率来实现。 后一种方法的优点在于它仅暂时增加了“接通”电阻，这在瞬时之后不会引起任何余量问题。 具体应用是可编程逻辑集成电路的差分输出。

公开(公告)号：US06888370B1

公开(公告)日：2005-05-03

申请号：US10645932

申请日：2003-08-20

申请人： Mei Luo ,  Wilson Wong ,  Sergey Shumarayev

发明人： Mei Luo ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03K19/0175 ,  H04L25/02

CPC分类号： H04L25/0278

摘要： The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.

摘要翻译： 片内阻抗终端电路可以动态调节，以匹配传输线阻抗值。 集成电路上的终端电阻网络为耦合到IO引脚的传输线提供终端阻抗。 终端电阻器串联耦合并且彼此并联。 通孔与电阻耦合。 传递门单独接通或断开以将电阻与传输线耦合或去耦。 每个通过门被设置为ON或OFF以向传输线提供所选择的终端电阻值。 可以增加或减少电阻网络的终端电阻以匹配不同传输线路的阻抗。 也可以改变终端电阻以补偿由集成电路上的温度变化或其他因素引起的电阻器的变化。

公开(公告)号：US20050066429A1

公开(公告)日：2005-03-31

申请号：US10910873

申请日：2004-08-04

申请人： Wai Tang ,  Wilson Wong

发明人： Wai Tang ,  Wilson Wong

IPC分类号： A41D13/00 ,  A41D13/12 ,  A62B17/00

CPC分类号： A41D13/1263 ,  A41D13/0005 ,  A41D13/1218 ,  A62B17/001 ,  A62B17/006

摘要： A protective suit has a hood and a body having a neck opening. An annular connector connects the hood to the neck opening and has an annular groove for receiving an edge portion of the hood and/or body. A band extends along the groove upon the edge portion(s) to seal the same securely within the groove.

摘要翻译： 防护服有一个罩子和一个有颈部开口的身体。 环形连接器将发动机罩连接到颈部开口，并且具有用于容纳罩和/或主体的边缘部分的环形槽。 带在边缘部分沿着槽延伸以将其牢固地密封在槽内。

公开(公告)号：US06724222B2

公开(公告)日：2004-04-20

申请号：US10366814

申请日：2003-02-13

申请人： Rakesh H. Patel ,  John E. Turner ,  John D. Lam ,  Wilson Wong

发明人： Rakesh H. Patel ,  John E. Turner ,  John D. Lam ,  Wilson Wong

IPC分类号： H03K19175

CPC分类号： H03K19/018585 ,  H03K19/0027 ,  H03K19/00315 ,  H03K19/018521

摘要： A technique and circuitry interfaces a programmable logic integrated circuit compatible with one voltage level to other integrated circuits compatible with a different voltage level. In particular, an on-chip voltage less than the external supply level of the programmable logic integrated circuit is provided to a core portion of a programmable logic integrated circuit by way of a conversion transistor. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. Externally, the programmable logic integrated circuit will interface with an external supply voltage level. The input and output signals to and from the programmable logic integrated circuit will be compatible with the external supply level.

摘要翻译： 技术和电路将与一个电压电平兼容的可编程逻辑集成电路与不同电压电平兼容的其他集成电路接口。 特别地，通过转换晶体管将可编程逻辑集成电路的小于外部电源电平的片上电压提供给可编程逻辑集成电路的核心部分。 在一个实施例中，转换晶体管的布局（或物理结构）分布在芯部分周围。 在外部，可编程逻辑集成电路将与外部电源电压接口。 来自可编程逻辑集成电路的输入和输出信号将与外部电源电平兼容。

公开(公告)号：US06583646B1

公开(公告)日：2003-06-24

申请号：US09860028

申请日：2001-05-16

申请人： Rakesh H. Patel ,  John E. Turner ,  Wilson Wong

发明人： Rakesh H. Patel ,  John E. Turner ,  Wilson Wong

IPC分类号： H03K190175

CPC分类号： H03K19/018585 ,  H03K19/0027 ,  H03K19/00315 ,  H03K19/018521

摘要： An input/output driver for interfacing directly with a voltage at a pad which is above a supply voltage for the input/output driver. This may be referred to as an “overvoltage condition.” For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator for preventing leakage current paths.

摘要翻译： 一个输入/输出驱动器，用于直接与焊盘上的电压进行接口，该电压高于输入/输出驱动器的电源电压。 这可能被称为“过电压条件”。 例如，如果电源电压为3.3V，则可以在输入/输出驱动器的焊盘处提供5V电压信号。 输入/输出驱动器将容忍该电压电平并防止漏电流路径。 这将提高集成电路的性能，可靠性和使用寿命。 输入/输出驱动器包括用于防止漏电流路径的阱偏置发生器。

公开(公告)号：US06563343B1

公开(公告)日：2003-05-13

申请号：US10136944

申请日：2002-04-30

申请人： Rakesh H. Patel ,  John E. Turner ,  John D. Lam ,  Wilson Wong

发明人： Rakesh H. Patel ,  John E. Turner ,  John D. Lam ,  Wilson Wong

IPC分类号： H03K190175

CPC分类号： H03K19/018585 ,  H03K19/0027 ,  H03K19/00315 ,  H03K19/018521

摘要： A technique provides an on-chip voltage to a core portion of an integrated circuit by way of a conversion transistor. The on-chip voltage may be a reduced internal voltage, less than the VCC of the integrated circuit. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. By providing the core with a reduced voltage, the integrated circuit may interface with other integrated circuits compatible with different voltage levels.

摘要翻译： 一种技术通过转换晶体管向集成电路的核心部分提供片上电压。 片上电压可能是内部电压降低，小于集成电路的VCC。 在一个实施例中，转换晶体管的布局（或物理结构）分布在芯部分周围。 通过为内核提供降低的电压，集成电路可以与与不同电压电平兼容的其他集成电路接口。

公开(公告)号：US06414518B1

公开(公告)日：2002-07-02

申请号：US09449166

申请日：1999-11-24

申请人： Rakesh H. Patel ,  John E. Turner ,  John D. Lam ,  Wilson Wong

发明人： Rakesh H. Patel ,  John E. Turner ,  John D. Lam ,  Wilson Wong

IPC分类号： H03K1900

CPC分类号： H03K19/018585 ,  H03K19/0027 ,  H03K19/00315 ,  H03K19/018521

摘要： A technique provides an on-chip voltage to a core portion of an integrated circuit by way of a conversion transistor. The on-chip voltage may be a reduced internal voltage, less than the VCC of the integrated circuit. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. By providing the core with a reduced voltage, the integrated circuit may interface with other integrated circuits compatible with different voltage levels.

摘要翻译： 一种技术通过转换晶体管向集成电路的核心部分提供片上电压。 片上电压可能是内部电压降低，小于集成电路的VCC。 在一个实施例中，转换晶体管的布局（或物理结构）分布在芯部分周围。 通过为内核提供降低的电压，集成电路可以与与不同电压电平兼容的其他集成电路接口。

公开(公告)号：US08754794B1

公开(公告)日：2014-06-17

申请号：US13558136

申请日：2012-07-25

申请人： Wei Li ,  Weiqi Ding ,  Wilson Wong

发明人： Wei Li ,  Weiqi Ding ,  Wilson Wong

IPC分类号： H03M1/10

CPC分类号： H03M1/1057 ,  H03M1/1028 ,  H03M1/164

摘要： An integrated circuit with a pipeline analog-to-digital (A/D) converter and associated calibration circuitry is provided. The A/D converter may include multiple series-connected pipeline stages at least some of which are implemented using a switched capacitor configuration. The calibration circuitry may include an analog error correction circuit, a digital error correction circuit, and a calibration control circuit for coordinating the operation of the analog and digital error correction circuits. During calibration operations, the analog error correction circuit may be used to suitably adjust a gain setting for each pipeline stage, whereas the digital error correction circuit may be used to compute a code offset value for each pipeline stage. Calibration may proceed from a least-significant-bit pipeline stage towards a most-significant-bit pipeline stage, one stage at a time.

摘要翻译： 提供了具有管线模数（A / D）转换器和相关校准电路的集成电路。 A / D转换器可以包括多个串联连接的流水线级，其中至少一些使用开关电容器配置来实现。 校准电路可以包括模拟误差校正电路，数字误差校正电路和用于协调模拟和数字纠错电路的操作的校准控制电路。 在校准操作期间，可以使用模拟错误校正电路来适当地调整每个流水线级的增益设置，而数字纠错电路可以用于计算每个流水线级的代码偏移值。 校准可以从最低有效位流水线阶段进入最高有效位流水线阶段，一次一个阶段。