公开(公告)号：US06888370B1

公开(公告)日：2005-05-03

申请号：US10645932

申请日：2003-08-20

申请人： Mei Luo ,  Wilson Wong ,  Sergey Shumarayev

发明人： Mei Luo ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03K19/0175 ,  H04L25/02

CPC分类号： H04L25/0278

摘要： The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.

摘要翻译： 片内阻抗终端电路可以动态调节，以匹配传输线阻抗值。 集成电路上的终端电阻网络为耦合到IO引脚的传输线提供终端阻抗。 终端电阻器串联耦合并且彼此并联。 通孔与电阻耦合。 传递门单独接通或断开以将电阻与传输线耦合或去耦。 每个通过门被设置为ON或OFF以向传输线提供所选择的终端电阻值。 可以增加或减少电阻网络的终端电阻以匹配不同传输线路的阻抗。 也可以改变终端电阻以补偿由集成电路上的温度变化或其他因素引起的电阻器的变化。

公开(公告)号：US07675326B1

公开(公告)日：2010-03-09

申请号：US12163709

申请日：2008-06-27

申请人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

发明人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

IPC分类号： H03K19/094

CPC分类号： H03K19/00369 ,  H03K19/01812 ,  H03K19/01837 ,  H03K19/018514 ,  H03K19/018585

摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

摘要翻译： 使用动态可调差分输出驱动器提供系统和方法。 诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。 可以调整输出驱动器的峰峰值输出电压和共模电压。 动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。 基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

公开(公告)号：US07397270B1

公开(公告)日：2008-07-08

申请号：US11138919

申请日：2005-05-25

申请人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

发明人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

IPC分类号： H03K19/094

CPC分类号： H03K19/00369 ,  H03K19/01812 ,  H03K19/01837 ,  H03K19/018514 ,  H03K19/018585

摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

摘要翻译： 使用动态可调差分输出驱动器提供系统和方法。 诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。 可以调整输出驱动器的峰峰值输出电压和共模电压。 动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。 基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

公开(公告)号：US06943588B1

公开(公告)日：2005-09-13

申请号：US10670146

申请日：2003-09-24

申请人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

发明人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

IPC分类号： H03K19/094

CPC分类号： H03K19/00369 ,  H03K19/01812 ,  H03K19/01837 ,  H03K19/018514 ,  H03K19/018585

摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

摘要翻译： 使用动态可调差分输出驱动器提供系统和方法。 诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。 可以调整输出驱动器的峰峰值输出电压和共模电压。 动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。 基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

公开(公告)号：US07176710B1

公开(公告)日：2007-02-13

申请号：US11093188

申请日：2005-03-28

申请人： Mei Luo ,  Wilson Wong ,  Sergey Shumarayev

发明人： Mei Luo ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03K19/175

CPC分类号： H04L25/0278

摘要： The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.

摘要翻译： 片内阻抗终端电路可以动态调节，以匹配传输线阻抗值。 集成电路上的终端电阻网络为耦合到IO引脚的传输线提供终端阻抗。 终端电阻器串联耦合并且彼此并联。 通孔与电阻耦合。 传递门单独接通或断开以将电阻与传输线耦合或去耦。 每个通过门被设置为ON或OFF以向传输线提供所选择的终端电阻值。 可以增加或减少电阻网络的终端电阻以匹配不同传输线路的阻抗。 也可以改变终端电阻以补偿由集成电路上的温度变化或其他因素引起的电阻器的变化。

公开(公告)号：US08836443B2

公开(公告)日：2014-09-16

申请号：US13617347

申请日：2012-09-14

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

IPC分类号： H01L23/66 ,  H03B5/08 ,  H03C3/22 ,  H01F27/29 ,  H03B5/12 ,  H01F27/28 ,  H01F21/12

CPC分类号： H03B5/1212 ,  H01F2021/125 ,  H01F2027/2809 ,  H01L2924/0002 ,  H03B5/1243 ,  H03B5/1268 ,  H01L2924/00

摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

摘要翻译： 提供具有锁相环的集成电路。 锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。 压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。 多个电感器中选择的一个可以主动地连接到振荡器电路。 压控振荡器可以具有多个振荡器电路。 每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。 每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。 所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

公开(公告)号：US08406258B1

公开(公告)日：2013-03-26

申请号：US12752984

申请日：2010-04-01

申请人： Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

发明人： Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

IPC分类号： H04J3/06

CPC分类号： H03M9/00 ,  H03K19/1776 ,  H04J3/047 ,  H04J3/0685

摘要： One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及一种集成电路，其包括多个通信信道，每个信道中的时钟多路复用器，两个低抖动时钟发生器电路和时钟分配电路。 每个通道包括被布置为使用参考时钟信号传送串行数据流的电路，并且每个通道中的时钟复用器被配置为从多个输入时钟信号中选择参考时钟信号。 第一低抖动时钟发生器电路被布置为使用第一基于电感器 - 电容器的振荡器电路产生第一时钟信号，并且第二低抖动时钟发生器电路被布置为使用第二电感器电容器产生第二时钟信号 基振荡电路基于第一和第二电感电容器的振荡电路具有不同的调谐范围。 时钟分配电路被布置为将第一和第二低抖动时钟信号输入到每个所述时钟多路复用器。 还公开了其它实施例和特征。

公开(公告)号：US08299802B2

公开(公告)日：2012-10-30

申请号：US12263290

申请日：2008-10-31

申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

IPC分类号： G01R31/02

CPC分类号： G01R31/3167

摘要： An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.

摘要翻译： 提出了一种能够监视模拟模块内的模拟电压的集成电路。 集成电路具有模拟测试复用器（多路复用器），其输入端连接到模拟模块内的感兴趣的模拟电压。 模拟测试复用器将选定的模拟电压从模拟模块引导到模拟测试复用器的输出。 集成电路还包括模拟监视状态机，其向模拟测试多路复用器提供选择位，使得能够随机访问模拟块内的模拟电压。 集成电路还包括用于将来自模拟测试多路复用器的所选模拟电压转换为数字表示的模数转换器。

公开(公告)号：US08184651B2

公开(公告)日：2012-05-22

申请号：US12100360

申请日：2008-04-09

申请人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

发明人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding

IPC分类号： H04L12/56

CPC分类号： H04L49/30 ,  H04L49/352

摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10 GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10 GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.

摘要翻译： 集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10千兆以太网（10GbE）收发器电路。 可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。 该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。 将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

公开(公告)号：US08120429B1

公开(公告)日：2012-02-21

申请号：US12787722

申请日：2010-05-26

申请人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

发明人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

IPC分类号： H03L7/00 ,  H03K3/03

CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K3/35613 ,  H03K2005/00228 ,  H03K2005/00234

摘要： Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.

摘要翻译： 提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。 本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。 一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。 电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。 该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。